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US20120317529 Rapid Estimation of Temperature Rise in Wires Due to Joule Heating  
A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self...
US20140089879 CHARACTERIZATION BASED BUFFERING AND SIZING FOR SYSTEM PERFORMANCE OPTIMIZATION  
A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an...
US20150169819 DESIGN RULE CHECKING FOR CONFINING WAVEFORM INDUCED CONSTRAINT VARIATION IN STATIC TIMING ANALYSIS  
A method for design rule checking (DRC) during static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating...
US20150135153 METHOD OF VALIDATING TIMING ISSUES IN GATE-LEVEL SIMULATION  
A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the...
US20130275935 PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS  
An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an...
US20100306724 METHOD OF INCREMENTAL STATISTICAL STATIC TIMING ANALYSIS BASED ON TIMING YIELD  
Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit,...
US20120240090 CLOCK TREE DESIGNING APPARATUS AND CLOCK TREE DESIGNING METHOD  
A clock tree designing apparatus in an embodiment includes: an equidistant point set calculation section configured to set a path setting block area in which a path length of a clock path takes a...
US20150248519 SYSTEM FOR PARTITIONING INTEGRATED CIRCUIT DESIGN BASED ON TIMING SLACK  
A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a...
US20140258954 RANKING VERIFICATION RESULTS FOR ROOT CAUSE ANALYSIS  
Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of...
US20150121327 MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) CROSS-TIER CLOCK SKEW MANAGEMENT SYSTEMS, METHODS AND RELATED COMPONENTS  
Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary...
US20120124537 SLACK-BASED TIMING BUDGET APPORTIONMENT  
A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential...
US20130061191 AUTOMATED FUNCTIONAL COVERAGE FOR AN INTEGRATED CIRCUIT DESIGN  
A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a...
US20120215516 IR Drop Analysis in Integrated Circuit Timing  
In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the...
US20140130001 Method of Reducing Parasitic Mismatch  
A method of reducing parasitic mismatches comprises generating a first net list file from a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism using a first...
US20120144358 Resolving Global Coupling Timing and Slew Violations for Buffer-Dominated Designs  
A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being...
US20140149956 CORNER SPECIFIC NORMALIZATION OF STATIC TIMING ANALYSIS  
A method and a system for expressing results of a timing analysis of an integrated circuit (IC) chip design as relative values to drive efficient chip design closure include: using a computer,...
US20110035717 Design Optimization for Circuit Migration  
An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium...
US20140089881 Circuit Timing Analysis Incorporating the Effects of Temperature Inversion  
Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing...
US20120210287 Circuit Timing Analysis Incorporating the Effects of Temperature Inversion  
Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing...
US20120180015 SYSTEM AND METHOD FOR METASTABILITY VERIFICATION OF CIRCUITS OF AN INTEGRATED CIRCUIT  
A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For...
US20120117527 PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS  
In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for...
US20130159953 PERFORMING STATISTICAL TIMING ANALYSIS WITH NON-SEPARABLE STATISTICAL AND DETERMINISTIC VARIATIONS  
In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for...
US20130097567 CYCLE CUTTING WITH TIMING PATH ANALYSIS  
The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by...
US20120144359 CYCLE CUTTING WITH TIMING PATH ANALYSIS  
The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by...
US20140337813 METHOD AND APPARATUS FOR EXTRACTING DELAY PARAMETER  
A delay parameter extracting apparatus includes a schematic composing unit, a layout composing unit, a verification unit, and a parameter extracting unit. The schematic composing unit is...
US20130298097 METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER  
A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit,...
US20120131531 Reducing Leakage Power in Integrated Circuit Designs  
A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is...
US20120324411 INTEGRATED CIRCUIT OPTIMIZATION MODELING TECHNOLOGY  
A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit...
US20150040089 NUMERICAL AREA RECOVERY  
Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order,...
US20140040844 Method for Achieving An Efficient Statistical Optimization of Integrated Circuits  
Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis...
US20120192136 ORDERING OF STATISTICAL CORRELATED QUANTITIES  
Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing...
US20150121328 PATH-BASED FLOORPLAN ANALYSIS  
Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing...
US20120284681 CIRCUIT DESIGNING METHOD AND CIRCUIT DESIGNING SYSTEM  
A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The...
US20120017190 IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME  
An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic...
US20110289465 Statistical On-Chip Variation Timing Analysis  
A statistical on-chip variation approach to timing analysis permits the automated or semi-automated selection of design-specific margins without requiring complex statistical libraries. By...
US20130263075 UTILIZING GATE PHASES FOR CIRCUIT TUNING  
Implementing circuit tuning post design of an integrated circuit utilizing gate phases. Each phase includes a designation of one of a slow phase and a fast phase. During the circuit design phase,...
US20150220674 Detailed Placement with Search and Repair  
A method of detailed placement for ICs is provided. The method receives an initial placement and iteratively builds sets of constraints for placement of different groups of cells in the IC design...
US20120192135 METHODS FOR ANALYZING CELLS OF A CELL LIBRARY  
Methods and systems are provided for analyzing cells of a cell library used to generate a layout. One exemplary method involves determining a routed connection location utilized in the layout for...
US20130104092 METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR PERFORMING A PARAMETERIZED STATISTICAL STATIC TIMING ANALYSIS (SSTA) OF AN INTEGRATED CIRCUIT TAKING INTO ACCOUNT SETUP AND HOLD MARGIN INTERDEPENDENCE  
In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g.,...
US20120204138 CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN  
A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first...
US20150033198 INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT FOR RETIMING  
A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design,...
US20120131530 PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION  
A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference...
US20140298281 METHOD OF GLOBAL DESIGN CLOSURE AT TOP LEVEL AND DRIVING OF DOWNSTREAM IMPLEMENTATION FLOW  
System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design...
US20150040090 DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS  
Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell,...
US20140059508 Determining A Design Attribute By Estimation And By Calibration Of Estimated Value  
A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of...
US20110113396 DETERMINING A DESIGN ATTRIBUTE BY ESTIMATION AND BY CALIBRATION OF ESTIMATED VALUE  
A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of...
US20150154331 ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS  
A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of...
US20130275936 INTEGRATED CIRCUIT POWER MANAGEMENT VERIFICATION METHOD  
A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a...
US20090064070 SEMICONDUCTOR CIRCUIT DESIGN METHOD  
This disclosure concerns a semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop by using a computer. The semiconductor circuit design method...
US20150242559 PLACEMENT AWARE FUNCTIONAL ENGINEERING CHANGE ORDER EXTRACTION  
A computer implemented method for designing an integrated circuit includes receiving a netlist; receiving physical layout information related to an integrated circuit based on the on the netlist;...