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US20150067625 MACHINE-LEARNING BASED DATAPATH EXTRACTION  
A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster...
US20140372960 MACHINE-LEARNING BASED DATAPATH EXTRACTION  
A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster...
US20150058819 Interposer Defect Coverage Metric and Method to Maximize the Same  
Provided is a method of assigning a first set of probe pads to an interposer for maximizing a defect coverage for the interposer. The interposer includes a second set of nets and the defect...
US20130185687 PARAMETERIZED CELL LAYOUT GENERATION GUIDED BY A DESIGN RULE CHECKER  
A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a...
US20130212547 METHOD OF EXTRACTING BLOCK BINDERS AND AN APPLICATION IN BLOCK PLACEMENT FOR AN INTEGRATED CIRCUIT  
A method is directed to automatic extraction of block binders before block placement and application of block binders in block placement of an integrated circuit. Having block binders reduces the...
US20140351777 PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS  
A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and...
US20130019219 SYSTEM AND METHOD FOR HIERARCHY RECONSTRUCTION FROM FLATTENED GRAPHIC DATABASE SYSTEM LAYOUT  
System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an...
US20120117526 COMPUTER READABLE NON-TRANSITORY MEDIUM STORING DESIGN AIDING PROGRAM, DESIGN AIDING APPARATUS, AND DESIGN AIDING METHOD  
A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition...
US20140304670 RC Corner Solutions for Double Patterning Technology  
A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The...
US20150154339 Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells using Filters  
Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy...
US20140282325 Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells using Filters  
Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy...
US20150100935 METHOD OF DETERMINING IF LAYOUT DESIGN IS N-COLORABLE  
A method of determining if a layout design for fabricating a layer of features of an integrated circuit is N-colorable, comprising identifying a set of candidate cells among layout cells of a...
US20120284681 CIRCUIT DESIGNING METHOD AND CIRCUIT DESIGNING SYSTEM  
A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The...
US20100325597 GENERALIZED CONSTRAINT COLLECTION MANAGEMENT METHOD  
Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design...
US20130198705 CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY  
In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second...
US20090265673 INTERSECT AREA BASED GROUND RULE FOR SEMICONDUCTOR DESIGN  
A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in...
US20110265053 METHOD AND SOFTWARE FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT  
In order to improve a failure detection rate in a layout automatic design process of a DFT circuit, signal lines of the DFT circuit are aggregated by an AND tree circuit 1 or an OR tree circuit...
US20120159412 TRANSISTOR-LEVEL LAYOUT SYNTHESIS  
A layout tool partially replicates the layout of a base cell to determine the layout for a target cell. The base cell is information representing an arrangement of a set of transistors having an...
US20150154341 SYSTEMS AND METHODS FOR SPECIFYING. MODELING, IMPLEMENTING AND VERIFYING IC DESIGN PROTOCOLS  
A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC)...
US20110197173 POLISHING ESTIMATION/EVALUATION DEVICE, OVERPOLISHING CONDITION CALCULATION DEVICE, AND COMPUTER-READABLE NON-TRANSITORY MEDIUM THEREOF  
A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit...
US20120278776 SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN  
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET...
US20080016486 System and method of assessing reliability of a semiconductor  
A system for assessing reliability of a semiconductor product design, the system comprising a first database for storing circuits data specifying cells of available circuits for semiconductor...
US20120304138 CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY  
A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one...
US20080022253 Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information  
A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each...
US20110016444 Collaborative Environment For Physical Verification Of Microdevice Designs  
A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results...
US20150082265 DESIGN STRUCTURE FOR CHIP EXTENSION  
One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second...
US20120278777 SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN  
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET...
US20130275934 SOLVING CONGESTION USING NET GROUPING  
A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected...
US20130055183 3D INTER-STRATUM CONNECTIVITY ROBUSTNESS  
There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D...
US20120304139 METHOD OF FAST ANALOG LAYOUT MIGRATION  
A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist...
US20140354338 LENGTH-OF-DIFFUSION PROTECTED CIRCUIT AND METHOD OF DESIGN  
A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.
US20140229907 AUTOMATED SCALABLE VERIFICATION FOR HARDWARE DESIGNS AT THE REGISTER TRANSFER LEVEL  
A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting...
US20150067624 SYSTEM AND METHOD FOR LEAKAGE ESTIMATION FOR STANDARD INTEGRATED CIRCUIT CELLS WITH SHARED POLYCRYSTALLINE SILICON-ON-OXIDE DEFINITION-EDGE (PODE)  
A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage...
US20130125075 METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY  
An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout...
US20150135151 Canonical Forms Of Layout Patterns  
Aspects of the disclosed technology relate to techniques for determining canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first...
US20130339915 CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES  
A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical...
US20090049416 Computer Program Product for Extending Incremental Verification of Circuit Design to Encompass Verification Restraints  
An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for...
US20140068534 Designing Photonic Switching Systems Utilizing Equalized Drivers  
Designing a photonics switching system is provided. A photonic switch diode is designed to attain each performance metric in a plurality of performance metrics associated with a photonic switching...
US20110016445 Layout design system and layout design method  
In a layout design of a semiconductor circuit, by selecting a frequently-used layout cell based on a layout design, a common location (coordinate) at which dummy metal is arranged is specified. A...
US20090125855 Forming Separation Directives Using A Printing Feasibility Analysis  
Separation directives for integrated circuit layout design data are formed based upon one or more printing feasibility analyses performed on the layout design data. At least one printing...
US20090254873 CIRCUIT BOARD ANALYZER AND ANALYSIS METHOD  
A circuit board analyzer includes a storage unit for storing mesh position information on an analyzed mesh-division model and extracted circuit constants in relation to each other; a...
US20120198402 SYSTEMS AND METHODS FOR MAPPING STATE ELEMENTS OF DIGITAL CIRCUITS FOR EQUIVALENCE VERIFICATION  
Systems and methods for mapping state elements of digital circuits for equivalence verification are provided. One method for mapping state elements for equivalence verification between a first...
US20100192113 METHOD AND APPARATUS FOR MANAGING VIOLATIONS AND ERROR CLASSIFICATIONS DURING PHYSICAL VERIFICATION  
Some embodiments provide a system for managing violations during physical verification. The system may identify a design-rule-check (DRC) violation by applying a set of DRC rules to a layout. The...
US20140157213 METHOD OF GENERATING A SET OF DEFECT CANDIDATES FOR WAFER  
A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes...
US20080098340 Method for Designing Block Placement and Power Distribution of Semiconductor Integrated Circuit  
The present invention relates to a method for designing initial placement of functional blocks and designing power distribution network of a semiconductor integrated circuit in the next stage of...
US20120060135 Integrated Circuit Transformer Devices for On-Chip Millimeter-Wave Applications  
Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit...
US20120124538 METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT  
A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add...
US20100095256 Power State Transition Verification For Electronic Design  
Various implementations of the invention may be applied to generate an auxiliary verification statement. The auxiliary verification statement defines properties that may be employed to check if...
US20130227509 PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS  
A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which...
US20110138346 MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING  
The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false...

Matches 1 - 50 out of 231 1 2 3 4 5 >