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US20060230377 Computer-based tool and method for designing an electronic circuit and related system  
A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an...
US20050060676 Semiconductor integrated circuit and method for designing same  
The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included...
US20060253822 Semiconductor integrated circuit and method for designing same  
The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included...
US20070033554 Delay distribution calculation method, circuit evaluation method and false path extraction method  
Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving...
US20080172646 Array transformation in a behavioral synthesis tool  
A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate variables or arrays to memory...
US20160188774 Circuit Design and Optimization  
A method implemented on a data processing system for circuit design is described. The method comprises identifying one or more first portions of a design of a circuit, each of the one or more...
US20060253823 Semiconductor integrated circuit and method for designing same  
The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included...
US20050273683 Insertion of embedded test in RTL to GDSII flow  
A method of designing a scan testable integrated circuit with embedded test objects for use in scan testing the circuit, comprises compiling a register-transfer level (RTL) circuit description of...
US20110145775 CELL LIBRARY, LAYOUT METHOD, AND LAYOUT APPARATUS  
In a cell library that is used for layout design of a semiconductor integrated circuit and is a library of design data of cells each realizing a unit function, each of the design data includes...
US20080092093 Register Transfer Level (RTL) Test Point Insertion Method to Reduce Delay Test Volume  
A method includes inserting test points into a circuit for reducing the number of specified bits required for transition fault testing of the circuit by reducing the dependency of a second...
US20080129362 SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING SEMICONDUCTOR DEVICE  
A semiconductor device designing method of the present invention corresponds to a method for designing a clock synthesization type semiconductor device, which is comprised of: a rough CTS (clock...
US20060080626 Visualization method and apparatus for logic verification and behavioral analysis  
A logic verification tool detects and flags a logic operation with high probability to cause a fault in an electronic system. An efficient logic debug method utilizes a partial sequence of signal...
US20070074141 Simulation apparatus and simulation method  
According to an aspect of the invention, a simulation apparatus includes: a computer configured to execute a program which is formed as an operating description having no temporal restriction; and...
US20070220468 Method and Apparatus for Converting Globally Clock-Gated Circuits to Locally Clock-Gated Circuits  
A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a...
US20070089076 Application of consistent cycle context for related setup and hold tests for static timing analysis  
A technique for performing static timing analysis of an integrated circuit design provides a relationship between reference events of a setup test and a hold test for a particular signal path of...
US20070074137 Database and method of verifying function of LSI using the same  
Provided is a method of verifying the function of the LSI including: a first signal database generating step of registering a first signal data set for associating a first verification target...
US20080066035 Method and design system of semiconductor integrated circuit  
Disclosed is a design method for optimizing the timings at which a plurality of power supply switches in a power gating circuit in a semiconductor integrated circuit by the steps of (A) providing...
US20070226671 Apparatus and method of static timing analysis considering the within-die and die-to-die process variation  
In a method and apparatus for designing semiconductor integrated circuit, a path delay information producing section produces path delay information by performing a static timing analysis based on...
US20070101302 Mixed signal circuit simulator  
The waveform created by a circuit simulator is selected. The input data 11 inputted by an inputting means are obtained for a point on the waveform or the waveform. The selected waveform and the...
US20050144580 Method and system for testing a logic design  
A method of testing a logic design in one disclosed embodiment includes identifying a plurality of clocked logic elements of a first logic design. The plurality of logic elements is subdivided...
US20050188336 System and method for waiving a verification check  
A system and method for waiving a verification check associated with a circuit design. In one embodiment, a first engine integrates waiver options associated with the circuit design's design...
US20100313176 DELAY LIBRARY, DELAY LIBRARY CREATION METHOD, AND DELAY CALCULATION METHOD  
A timing window (TW) representing a time zone where a signal transition possibly occurs in a time axis is generated for each of input signals in input terminals in a multi-input logic cell based...
US20080098336 Compiler and logic circuit design method  
A compiler in which pseudo C descriptions (1) that are capable of describing parallel operations at a statement level and at a cycle precision by clock boundaries and register assignment...
US20050149895 Delay library generation method and delay library generation device  
A delay library of high accuracy is efficiently generated within a short time period. To this end, a set-up time is calculated by static analysis with no consideration of a delay caused by a wire;...
US20050034090 Circuit designing method and a circuit designing system  
A circuit designing method includes steps (a) to (d). The step (a) separates a first algorithm description for a simulation into a hardware portion describing hardware and a software portion...
US20050086621 Method for processing design data of semiconductor integrated circuit  
A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do...
US20080092092 Method and Processor for Power Analysis in Digital Circuits  
This invention relates to a method and processor (19) for power analysis in digital circuits. The method incorporates a main processor (19) and an associative memory mechanism (101a, 101b, 102,...
US20060236284 Design method by estimating signal delay time with netlist created in light of terminal line in macro and program for creating the netlist  
A design method that implements automatic layout based on a first netlist created from a design circuit includes laying out a plurality of functional blocks of the design circuit based on the...
US20110296361 CIRCUIT ANALYSIS METHOD  
A maximum delay of a combinational circuit is accurately reduced in consideration of a correlation between variations in delays of devices (transistors etc.) and interconnects. Circuit...
US20080040700 Behavioral synthesizer, debugger, writing device and computer aided design system and method  
The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for...
US20050223345 Circuit design assistant system, circuit design method, and program product for circuit design  
The computer program product according to an embodiment of the invention causes a computer to execute the process including acquiring circuit information generated by behavioral synthesis,...
US20070168902 Method for high-level synthesis of semiconductor integrated circuit  
A Control Data Flow Graph (CDFG) which is an intermediate representation obtained by analyzing a behavioral-level circuit description of hardware, is subjected to a process of changing a shape of...
US20120008450 FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT  
A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data...
US20070271538 Process for designing a circuit for synchronizing data asychronously exchanged between two synchronous blocks, and synchronization circuit fabricated by same  
The process relates to the design of a circuit for synchronizing data asynchronously exchanged between two synchronous blocks. The circuit comprises at least one critical flip-flop capable of...
US20140040842 TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT  
A method of reducing total power dissipation for logic cells using Boolean equations includes selecting a path, identifying at least one group of logic cells for analysis in the path, and deriving...
US20070083830 Various methods and apparatuses for an executable parameterized timing model  
Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area and power constraints in an electronic design system. The IP Generator receives a...
US20060236279 Design supporting apparatus, design supporting method, and computer product  
A design supporting apparatus includes a detecting unit that detects a path constituting a circuit from circuit information of the circuit; a sensitivity-equation producing unit that produces a...
US20050091623 Method and apparatus for computer-aided creation of a clock tree structure file, a method for computer-aided creation of a layout for a semiconductor circuit, and a computer-readable storage media  
Method for computer-aided creation of a clock tree structure file for a semiconductor circuit, which has a plurality of synchronously driven switching elements and a plurality of signal...
US20050091622 Method of grouping scan flops based on clock domains for scan testing  
A method of grouping cells in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) initializing a corresponding list of...
US20060026543 ACCURATE TIMING ANALYSIS OF INTEGRATED CIRCUITS WHEN COMBINATORIAL LOGIC OFFERS A LOAD  
The accuracy of timing analysis of an integrated circuit is enhanced based on an observation that the capacitive load offered by a combinatorial element (e.g., logic gate) is more when the value...
US20150033196 Clustering For Processing Of Circuit Design Data  
Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are...
US20140082573 CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND COMPUTER PRODUCT  
A circuit design support apparatus includes a processor configured to calculate a time period necessary for a transition of a logical state, based on circuit configuration information indicating...
US20070234253 Multiple mode approach to building static timing models for digital transistor circuits  
A method and a system for building static models for transistor circuit design is described. This method includes performing an automatic timing model construction several times on certain problem...
US20130097567 CYCLE CUTTING WITH TIMING PATH ANALYSIS  
The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by...
US20150193564 SYSTEM AND METHOD FOR USING CLOCK CHAIN SIGNALS OF AN ON-CHIP CLOCK CONTROLLER TO CONTROL CROSS-DOMAIN PATHS  
An on-chip clock controller configured to control cross-domain paths using clock chain signals is disclosed. The on-chip clock controller includes a clock bits module configured to receive a clock...
US20110204918 DELAY SIMULATION SYSTEM, DELAY SIMULATION METHOD, PLD MAPPING SYSTEM, PLD MAPPING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT  
A delay simulation system comprises an input unit configured to input a netlist, a library, and information including load capacitances; and a simulation unit; the library defines a plurality of...
US20060259885 System and method for analyzing a circuit  
A system and method for analyzing a circuit. In one embodiment, a tool generates path information based upon a netlist that describes the circuit. A synthesizer generates a nodal data structure...
US20140068533 INFORMATION THEORETIC SUBGRAPH CACHING  
Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more...
US20110191734 DESIGNING APPARATUS, DESIGNING METHOD, AND COMPUTER READABLE MEDIUM  
In general, according to one embodiment, a designing apparatus includes a clock tree generator, a logic modifier, a layout modifier, and an outputting module. The clock tree generator is...
US20080005709 VERIFICATION OF LOGIC CIRCUITS USING CYCLE BASED DELAY MODELS  
Methods and systems for verifying a logic circuit. In one embodiment, delay models based on clock cycles are developed and incorporated into the logic circuit so that timing considerations may be...

Matches 1 - 50 out of 79 1 2 >