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US20110283246 Method and Apparatus for Merging EDA Coverage Logs of Coverage Data  
An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as...
US20110022997 METHOD FOR CONJECTURING EFFECTIVE WIDTH AND EFFECTIVE LENGTH OF GATE  
A method for conjecturing the effective size, i.e. the effective width or effective length, of a gate is disclosed. First, a first design gate group including a first gate design width and a first...
US20120311513 METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION OF AN ELECTRONIC DESIGN  
Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the...
US20110185325 Navigating Analytical Tools Using Layout Software  
A background process is used to install at least one system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook,...
US20110035713 CIRCUIT BOARD DESIGN SYSTEM AND METHOD  
A method and system for designing a circuit board designs wiring of the circuit board, and determines electronic rules and physical rules of the wiring design. The method and system creates a...
US20130298093 Method of Predicting Contention Between Electronic Circuit Drivers  
Software method to identify presence of multiple digital drivers disposed in a manner that creates multiple conflicting current paths in complex electronic circuit designs. Digital drivers are...
US20120110528 METHOD OF PREDICTING ELECTRONIC CIRCUIT FLOATING GATES  
Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding...
US20120266118 Accelerating Coverage Convergence Using Symbolic Properties  
In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions...
US20110302541 Methods and Systems for Evaluating Checker Quality of a Verification Environment  
Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual...
US20110066989 METHOD AND SYSTEM TO AT LEAST PARTIALLY ISOLATE NETS  
A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the...
US20110185334 ZONE-BASED LEAKAGE POWER OPTIMIZATION  
A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate,...
US20130318486 METHOD AND SYSTEM FOR GENERATING VERIFICATION ENVIRONMENTS  
A method and system for a verification of a DUT is provided. The method and system is configured to generate a verification environment using a rules based metalanguage. The rules are converted...
US20110154280 PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY  
An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape...
US20140123089 MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING  
Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer...
US20110219344 Spatial Correlation-Based Estimation of Yield of Integrated Circuits  
Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of...
US20140215418 Digital Circuit Verification Monitor  
A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally...
US20130019217 Digital Circuit Verification Monitor  
A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally...
US20110320992 BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN  
A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit...
US20150135149 MONITORING COVERAGE FOR STATIC MODELLING OF AN ELECTRONIC DEVICE  
A design verification system automatically identifies coverage of different constraints for a static model of an electronic device. The static model can be employed by a tool, referred to as a...
US20130174107 DESIGN TOOL FOR GLITCH REMOVAL  
Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each...
US20110107281 TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN AUTOMATION  
Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered...
US20110154275 METHOD AND SYSTEM FOR DEFINING GENERIC TOPOLOGIES FOR USE IN TOPOLOGY MATCHING ENGINES  
Circuit analysis software packages are a significant tool used today in the design of integrated circuits (ICs). Many of the conventional and commercially available simulation or analysis...
US20110197170 Active Net Based Approach for Circuit Characterization  
In a circuit design method, a computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. The computer system extracts, from a layout of the...
US20100107130 1XN BLOCK BUILDER FOR 1XN VLSI DESIGN  
Embodiments that generate 1×N building block representations for an IC design via a GUI of a 1×N block builder are disclosed. Some embodiments enable, via a GUI, selection of a logical function...
US20080066029 METHOD AND SYSTEM ALERTING AN ENTITY TO DESIGN CHANGES IMPACTING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE IN A VIRTUAL FAB ENVIRONMENT  
A design coordination engine coordinates design implementation among a manufacturing facility, a customer, an IP vendor, and a design group during the design phase of a semiconductor device. The...
US20120096419 METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE AND DESIGN STRUCTURE  
A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit...
US20110093825 TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC  
A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is...
US20110047521 DEVELOPMENT TOOL FOR COMPARING NETLISTS  
System, method, and program product analyze netlists for related electrical circuit designs by comparing predefined physical characteristics between the netlists. A baseline reference score is...
US20150161306 FAULT INSERTION FOR SYSTEM VERIFICATION  
A computer implemented method of modifying a compiled design of an electronic circuit is disclosed. The method includes accessing a stored compilation representing the design, and causing the...
US20110161902 Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification  
A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, mulitple trace status tables are received, and each of the trace status tables...
US20120324409 ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION  
The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate...
US20150082262 DYNAMICALLY GENERATING JOG PATCHES FOR JOG VIOLATIONS  
Systems, methods, and other embodiments associated with dynamically generating jog patches are described. In one embodiment, a method includes determining a virtual edge within metal of a design...
US20130055178 THERMAL COUPLING DETERMINATION AND REPRESENTATION  
Thermal coupling effects are represented as current into a thermal node of an initial design structure. The current is determined using a thermal coupling coefficient, and thermal resistance and...
US20140282315 GRAPHICAL VIEW AND DEBUG FOR COVERAGE-POINT NEGATIVE HINT  
The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a...
US20130263071 APPARATUS AND METHOD TO COLLECT AND CONDENSE DESIGN VIOLATIONS FROM OUTPUT DATA FILES  
A method includes searching a plurality of lines of a log file for a violation of a defined condition; creating a database of all discovered violations; converting the database of all discovered...
US20120005640 METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT TWO LEVELS  
A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level,...
US20110093830 Integrated Circuit Optimization Modeling Technology  
A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit...
US20110113394 PWB Voltage and/or Current Calculation and Verification  
Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are laid out for a given design. Based on...
US20110173583 METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF  
A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in...
US20130086539 METHOD FOR CIRCUIT SIMULATION  
A circuit simulation method for checking a circuit error is disclosed. The method may include generating a netlist with respect to a designed circuit, simulating an operation of the designed...
US20130047129 Staged Scenario Generation  
A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device...
US20110239171 Staged Scenario Generation  
A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device...
US20110145771 Modeling for Soft Error Specification  
Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A...
US20090193369 PROCESS FOR DESIGN OF SEMICONDUCTOR CIRCUITS  
The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the...
US20070050738 Customer designed interposer  
A method and system that provides a customer with the ability to design an electrical connector (interposer) that is individualized to the customer's particular application requirements. An...
US20130074019 METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT TWO LEVELS  
A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level,...
US20110078642 Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine  
Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a...
US20070266349 DIRECTED RANDOM VERIFICATION  
A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested...
US20140040840 CONFLICT DETECTION WITH FUNCTION MODELS  
Systems and methods for detecting design conflicts of a product or process are disclosed. A method for detecting design conflicts includes processing a function model of a product or process to...
US20130318487 Programmable Circuit Characteristics Analysis  
Techniques for analysis of an electrical circuit design are described, which techniques employ two phases: an initialization phase, and a check phase. During the initialization phase, a circuit...