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US20150169792 COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN  
Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral...
US20130241597 INTEGRATED CIRCUIT WITH TIMING AWARE CLOCK-TREE AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT  
An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock...
US20130191801 DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS  
Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining...
US20130152029 DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS  
Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining...
US20130339914 TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS  
A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean...
US20120198394 Method For Improving Circuit Design Robustness  
Improving circuit design robustness is based on identifying process sensitive and design critical devices. Design critical devices are identified using circuit design information. Various...
US20120167023 METHOD FOR SYNTHESIZING TILE INTERCONNECTION STRUCTURE OF FIELD PROGRAMMABLE GATE ARRAY  
A method for synthesizing a tile interconnection structure of a field programmable gate array (FPGA) includes: receiving an interconnection structure specification of the FPGA; constructing a tile...
US20080288911 Method for localizing faulty hardware components and/or system errors within a production plant  
There is described a method for localizing faulty hardware components and/or system errors within a production plant comprising several hardware components, with the production plant and the...
US20110066992 Hardware Description Language (HDL) Generation Systems and Methods For Custom Circuit Boards  
A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from...
US20140280427 METHOD AND SYSTEM FOR DECOMPOSING SINGLE-QUBIT QUANTUM CIRCUITS INTO A DISCRETE BASIS  
A target quantum circuit expressed in a first quantum gate basis may be transformed into a corresponding quantum circuit expressed in a second quantum gate basis, which may be a universal set of...
US20120017186 SPECIFYING CIRCUIT LEVEL CONNECTIVITY DURING CIRCUIT DESIGN SYNTHESIS  
Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving...
US20120159408 IMPLEMENTATION OF FACTOR GRAPHS  
The process of implementing a belief propagation network in software and/or hardware can begin with a factor-graph-designer who designs a factor graph that implements that network. A development...
US20130145329 Incorporating Synthesized Netlists as Subcomponents in a Hierarchical Custom Design  
Mechanisms are provided for generating a physical layout of an integrated circuit design. A logic description of the integrated circuit design is received that comprises a first logic description...
US20090307638 TRUSTWORTHY STRUCTURAL SYNTHESIS AND EXPERT KNOWLEDGE EXTRACTION WITH APPLICATION TO ANALOG CIRCUIT DESIGN  
A system and method that does trustworthy multi-objective structural synthesis of analog circuits, and extracts expert analog circuit knowledge from the resulting tradeoffs. The system defines a...
US20140013289 GENERATING A CONVERGENT CIRCUIT DESIGN FROM A FUNCTIONAL DESCRIPTION USING ENTITIES HAVING ACCESS TO THE FUNCTIONAL DESCRIPTION AND TO PHYSICAL DESIGN INFORMATION  
A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each...
US20120089955 IMPLEMENTING ROUTING FIRST FOR RAPID PROTOTYPING AND IMPROVED WIRING OF HETEROGENEOUS HIERARCHICAL INTEGRATED CIRCUITS  
A method, system and computer program product are provided for implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuit chips....
US20140223397 Automatic Generation of Wire Tag Lists for a Metal Stack  
Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack...
US20130232458 Increasing PRPG-Based Compression By Delayed Justification  
An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with...
US20110231805 Increasing PRPG-Based Compression by Delayed Justification  
An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with...
US20130275930 SYNTHESIZING VHDL MULTIPLE WAIT FSMS INTO RT LEVEL FSMS BY PREPROCESSING  
Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process...
US20100318945 METHOD FOR N-VARIANT INTEGRATED CIRCUIT (IC) DESIGN, AND IC HAVING N-VARIANT CIRCUITS IMPLEMENTED THEREIN  
Techniques are generally described for designing an integrated circuit (IC). In various embodiments, the techniques include designing, at a functional specification level, N-variants of a...
US20140245242 VARIATION FACTOR ASSIGNMENT  
One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A...
US20140173538 FEC DECODER DYNAMIC POWER OPTIMIZATION  
A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity...
US20050273683 Insertion of embedded test in RTL to GDSII flow  
A method of designing a scan testable integrated circuit with embedded test objects for use in scan testing the circuit, comprises compiling a register-transfer level (RTL) circuit description of...
US20120304135 METHOD AND APPARATUS FOR PRECISION TUNABLE MACRO-MODEL POWER ANALYSIS  
A method for estimating power consumption of a target device upon designing the target device, includes: preparing a hybrid power library having a regression power library part and lookup-table...
US20130268903 Display and automatic improvement of timing and area in a network-on-chip  
A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit...
US20120311512 Display and automatic improvement of timing and area in a network-on-chip  
A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit...
US20120047476 CIRCUIT DESIGN OPTIMIZATION  
A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout...
US20150070048 VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES  
Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic...
US20130214380 AREA AND POWER SAVING STANDARD CELL METHODOLOGY  
A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at...
US20150234948 BOUNDARY BASED POWER GUIDANCE FOR PHYSICAL SYNTHESIS  
A method and system to obtain a physical design of an integrated circuit from a logical design are described. The method includes performing a baseline synthesis to obtain a baseline physical...
US20080250379 LOGIC CIRCUIT SYNTHESIS DEVICE  
In a logic circuit synthesis device, a library of cell preliminarily stores a condition concerning a property that should be satisfied by the net having the property. The logic circuit synthesis...
US20070277144 Conversion of circuit description to an abstract model of the circuit  
A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the...
US20110298010 Cell Library, Integrated Circuit, and Methods of Making Same  
A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second...
US20090100398 STRUCTURE FOR PERFORMING ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN TO ATTAIN POWER CLOSURE  
A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer...
US20130111425 POWER BALANCED PIPELINES  
Power balancing techniques are provided for improving power efficiency of pipelined processors. A design-level implementation can be incorporated during synthesis of pipeline clocks in which a...
US20110173584 REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION  
A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed,...
US20100042966 MULTIPLEXER IMPLEMENTATION  
Disclosed is a method of improving a synthesized circuit design comprising searching the synthesized circuit design for a first instance of a first pattern of gates. The first instance is removed...
US20120005638 Race Logic Synthesis for Large-Scale Integrated Circuit Designs  
Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) and/or ESL...
US20130074030 METHOD, COMPUTER PROGRAM AND COMPUTING SYSTEM FOR OPTIMIZING AN ARCHITECTURAL MODEL OF A MICROPROCESSOR  
A computer program for optimizing an architectural model of a microprocessor by configuring elements of the instruction set as nodes of the graph. The architectural model of a microprocessor...
US20130263069 OPTIMIZING LOGIC SYNTHESIS FOR ENVIRONMENTAL INSENSITIVITY  
Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a...
US20140237437 LOOK-UP BASED FAST LOGIC SYNTHESIS  
Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during...
US20130191800 TIMING CONSTRAINT GENERATING SUPPORT APPARATUS AND METHOD OF SUPPORTING GENERATION OF TIMING CONSTRAINT  
A timing constraint generating support apparatus includes a propagation unit that propagates, through a wire connecting the logic circuits, timing constraints set for the logic circuits by using...
US20080072206 Unrolling Hardware Design Generate Statements in a Source Window Debugger  
Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the...
US20130305199 IN-PLACE RESYNTHESIS AND REMAPPING TECHNIQUES FOR SOFT ERROR MITIGATION IN FPGA  
In-place resynthesis for static memory (SRAM) based Field Programmable Gate Arrays (FPGAs) toward reducing sensitivity to single event upsets (SEUs). Resynthesis and remapping are described which...
US20140153341 SEQUENTIAL ACCESS MEMORY WITH MASTER-SLAVE LATCH PAIRS AND METHOD OF OPERATING  
A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave...
US20080222595 METHOD OF ENGINEERING CHANGE TO SEMICONDUCTOR CIRCUIT EXECUTABLE IN COMPUTER SYSTEM  
A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical...
US20090288059 CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS  
Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages...
US20080040700 Behavioral synthesizer, debugger, writing device and computer aided design system and method  
The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for...
US20130263068 RELATIVE ORDERING CIRCUIT SYNTHESIS  
Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing...

Matches 1 - 50 out of 358 1 2 3 4 5 6 7 8 >