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US20130086537 Design Routability Using Multiplexer Structures  
Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of...
US20150169792 COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN  
Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral...
US20110307848 METHOD FOR PREPARING FOR AND FORMALLY VERIFYING A MODIFIED INTEGRATED CIRCUIT DESIGN  
A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated...
US20130326441 MACHINE-LEARNING BASED DATAPATH EXTRACTION  
A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster...
US20110219344 Spatial Correlation-Based Estimation of Yield of Integrated Circuits  
Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of...
US20120159407 Low Depth Circuit Design  
A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f′n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the...
US20130055174 METHOD FOR VERIFYING FUNCTIONAL EQUIVALENCE BETWEEN A REFERENCE IC DESIGN AND A MODIFIED VERSION OF THE REFERENCE IC DESIGN  
A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a...
US20110320991 HIERARCHIAL POWER MAP FOR LOW POWER DESIGN  
A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit...
US20110068423 PHOTODETECTOR WITH WAVELENGTH DISCRIMINATION, AND METHOD FOR FORMING THE SAME AND DESIGN STRUCTURE  
The disclosure relates generally to photodetectors and methods of forming the same, and more particularly to optical photodetectors. The photodetector includes a waveguide having a radius that...
US20130205271 MACRO TIMING ANALYSIS DEVICE, MACRO BOUNDARY PATH TIMING ANALYSIS METHOD AND MACRO BOUNDARY PATH TIMING ANALYSIS PROGRAM  
A macro timing analysis device comprises a netlist merging unit which merges a layout-implemented top netlist obtained by executing clock path distribution and layout processing with respect to a...
US20120131524 METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY  
A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and...
US20150213159 METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES  
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
US20130047127 METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES  
Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
US20120079438 INTEGRATED CIRCUIT DESIGN FRAMEWORK COMPRISING AUTOMATIC ANALYSIS FUNCTIONALITY  
An embodiment of an integrated circuit design framework comprises a user interface which automatically initializes a three-dimensional simulation tool for simulating or analyzing the...
US20140026108 METHOD AND SYSTEM FOR DECOMPOSING SINGLE-QUBIT QUANTUM CIRCUITS INTO A DISCRETE BASIS  
The current application is directed to methods and systems which transform a given single-qubit quantum circuit expressed in a first quantum-gate basis into a quantum-circuit expressed in a...
US20140331194 Method for manufacturing a chip from a system definition  
A method for manufacturing a chip from a system definition, the system definition describing a plurality of cells, buses and external I/O. The cell definitions are defined by providing two...
US20120233576 SCHEMATIC-BASED LAYOUT MIGRATION  
Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells...
US20140129998 HIERARCHICAL EQUIVALENCE CHECKING AND EFFICIENT HANDLING OF EQUIVALENCE CHECKS WHEN ENGINEERING CHANGE ORDERS ARE IN AN UNSHARABLE REGISTER TRANSFER LEVEL  
An apparatus, a hierarchical method of equivalence checking a circuit design and equivalency checking after engineering change orders in a circuit design are disclosed herein. In one embodiment, a...
US20100332206 METHOD FOR SIMULATING LEAKAGE DISTRIBUTION OF INTEGRATED CIRCUIT DESIGN  
A method is provided for simulating leakage distribution of integrated circuit design. The method analyzes a layout of the integrated circuit design to understand the groups of dimensions of the...
US20140298277 METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY  
Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for...
US20150074623 USER GREY CELL  
In various embodiments, a user grey cell is disclosed. The user grey cell comprises a simplified logical implementation of a black box cell identified in a software and/or hardware design. The...
US20140025325 Voltage Level-Shifting  
Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, a computer readable tangible medium stores instructions executable by a computer. The...
US20130162293 Soft Error Hard Electronics Layout Arrangement and Logic Cells  
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a...
US20120290992 LOGICAL CIRCUIT NETLIST REDUCTION AND MODEL SIMPLIFICATION USING SIMULATION RESULTS CONTAINING SYMBOLIC VALUES  
A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic...
US20140109028 Translating a User Design in a Configurable IC for Debugging the User Design  
Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user...
US20120117525 Translating a User Design in A Configurable IC for Debugging the User Design  
Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user...
US20150095861 METHOD FOR PRODUCING A DPA-RESISTANT LOGIC CIRCUIT  
In an application-specific integrated circuit (ASIC), a description of the logic circuit is formulated in a hardware description language and then converted into a description of a corresponding...
US20120227020 METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS  
A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device,...
US20120180011 Register Transfer Level Design Compilation Advisor  
Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of...
US20120216159 VERIFICATION TECHNIQUES FOR LIVENESS CHECKING OF LOGIC DESIGNS  
A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to...
US20050273683 Insertion of embedded test in RTL to GDSII flow  
A method of designing a scan testable integrated circuit with embedded test objects for use in scan testing the circuit, comprises compiling a register-transfer level (RTL) circuit description of...
US20060095824 Determining circuit behavior  
Systems, methodologies, media, and other embodiments associated with automatically determining circuit behavior are described. One exemplary system embodiment includes a data acquisition logic...
US20140181764 IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH DIGESTS  
One method implementation disclosed includes detecting matching leaf cells that have functionally identical designs (optionally, similar designs) and assigning matching names for the matching leaf...
US20130055175 SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY  
Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a...
US20120112244 VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE  
Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures...
US20140129999 METHOD FOR SELECTIVELY MODELING NARROW-WIDTH STACKED DEVICE PERFORMANCE  
An approach for methodology enabling a verification of IC designs that compensates for degraded performance due to a physical placement, particularly a stacked physical placement is disclosed. A...
US20120043622 PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE  
Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k...
US20120126292 HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE  
Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The...
US20150161313 CIRCUIT DESIGN EVALUATION WITH COMPACT MULTI-WAVEFORM REPRESENTATIONS  
A design tool can implement phase algebra based design evaluation to efficiently evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual...
US20090319962 AUTOMATED CONVERSION OF SYNCHRONOUS TO ASYNCHRONOUS CIRCUIT DESIGN REPRESENTATIONS  
Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a...
US20120260224 Digital Netlist Partitioning System For Faster Circuit Reverse-Engineering  
Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry...
US20080120581 Computer product for supporting design and verification of integrated circuit  
Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an...
US20080189671 HDL Design Structure for Integrating Test Structures into an Integrated Circuit Design  
A hardware description language (HDL) design structure for performing device-specific testing and acquiring parametric data on integrated circuits, such that each chip can be tested individually...
US20070277144 Conversion of circuit description to an abstract model of the circuit  
A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the...
US20130290917 SYSTEM AND METHODS FOR INFERRING HIGHER LEVEL DESCRIPTIONS FROM RTL TOPOLOGY BASED ON CONNECTIVITY PROPAGATION  
A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable...
US20130117720 COMPUTER PRODUCT FOR SUPPORTING DESIGN AND VERIFICATION OF INTEGRATED CIRCUIT  
Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an...
US20150121323 DETERMINING A QUALITY PARAMETER FOR A VERIFICATION ENVIRONMENT  
Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware...
US20070046282 Method and apparatus for semi-automatic generation of test grid environments in grid computing  
Generating a description of a test grid environment for use in a grid computing environment. A database containing a number of test snapshots is generated. Each test snapshot reflects a previously...
US20120167022 METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES  
A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible...
US20140019921 LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL  
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors....
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