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US20140310665 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING A COMMON HARDWARE DATABASE INTO A LOGIC CODE MODEL  
A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based common representation of a hardware...
US20130346926 Automatic optimal integrated circuit generator from algorithms and specification  
Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no...
US20130205269 SYSTEM AND METHOD FOR MANAGING TIMING MARGIN IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN PROCESS  
A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file,...
US20120079437 CIRCUIT DESIGN SYSTEMS FOR REPLACING FLIP-FLOPS WITH PULSED LATCHES  
A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an...
US20120192129 Compiler for Closed-Loop 1xN VLSI Design  
Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral...
US20120192128 Compiler for Closed-Loop 1xN VLSI Design  
Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral...
US20120072876 METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULATION AND VERIFICATION  
Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a...
US20120066655 ELECTRONIC DEVICE AND METHOD FOR INSPECTING ELECTRICAL RULES OF CIRCUIT BOARDS  
An electronic device and method for inspecting electrical rules of circuit boards includes selecting at least two design files that record electrical rules of the circuit boards and searching the...
US20130298090 NETWORK RESISTOR MODEL ANALYSIS TOOL  
The invention may be embodied in a network resistor model analysis tool for an Electrical Rule Checking (ERC) system. The network resistor model analysis tool typically includes, but need not be...
US20130152028 NATIVE THRESHOLD VOLTAGE SWITCHING  
A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated...
US20060026538 Relational database storage and retrieval of circuit element classifications  
Various embodiments of a system, method and database for storing circuit element classification information in a relational database are disclosed. One database embodiment comprises a block...
US20140351775 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A DEBUGGER USING A COMMON HARDWARE DATABASE  
A hardware model database is identified which stores a graph-based common representation of a hardware design that includes hardware module nodes each representative of a unique module of the...
US20130174107 DESIGN TOOL FOR GLITCH REMOVAL  
Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each...
US20140089872 METHOD OF PROVING FORMAL TEST BENCH FAULT DETECTION COVERAGE  
Some aspects of the present disclosure provide for a system and method to discover which parts of a design a formal test suite can detect faults in, and thus how much of a design structure is...
US20130007677 Method of implementing IEC 61131-3 control specification through verilog HDL description for modeling, simulation and synthesis of control logic configuration for integrated circuit implementation  
The present invention relates to a method of implementing an IEC 61131-3 control specification through Verilog HDL description comprising the steps of (a) creating user interface for the control...
US20130332895 METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF  
A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in...
US20140026108 METHOD AND SYSTEM FOR DECOMPOSING SINGLE-QUBIT QUANTUM CIRCUITS INTO A DISCRETE BASIS  
The current application is directed to methods and systems which transform a given single-qubit quantum circuit expressed in a first quantum-gate basis into a quantum-circuit expressed in a...
US20140282310 METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT  
A method of generating, based on a first netlist of an integrated circuit, a second netlist includes generating layout geometry parameters for at least a portion of the first netlist of the...
US20130298091 METHOD OF PERFORMING CIRCUIT SIMULATION AND GENERATING CIRCUIT LAYOUT  
A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated...
US20150221575 TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY  
A computer program product or hardware description language (“HDL”) design structure in a computer-aided design system for generating a functional design model of an integrated circuitry structure...
US20140189617 DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN LAYOUT  
Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an...
US20130227502 ALGORITHM OF CU INTERCONNECT DUMMY INSERTING  
The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is...
US20140310664 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING A SOURCE DATABASE INTO A COMMON HARDWARE DATABASE  
A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is a graph-based intermediate representation of a hardware...
US20120117524 REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT  
A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time...
US20110307235 EQUIVALENT CIRCUIT MODEL FOR MULTILAYER CHIP CAPACITOR, CIRCUIT CONSTANT ANALYSIS METHOD, PROGRAM, DEVICE, AND CIRCUIT SIMULATOR  
Improved equivalent circuits and circuit analysis using the same for a multiplayer capacitor are provided. In one aspect, the equivalent series capacitance C and part of the equivalent series...
US20140191408 BACKSIDE METAL GROUND PLANE WITH IMPROVED METAL ADHESION AND DESIGN STRUCTURES  
A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The...
US20140270050 DESIGN AND DEPLOYMENT OF CUSTOM SHIFT ARRAY MACRO CELLS IN AUTOMATED APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN FLOW  
An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of...
US20120131523 METHOD OF GENERATING AN INTELLECTUAL PROPERTY BLOCK DESIGN KIT, METHOD OF GENERATING AN INTEGRATED CIRCUIT DESIGN, AND SIMULATION SYSTEM FOR THE INTEGRATED CIRCUIT DESIGN  
The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for...
US20130145328 AUTOMATED SCALABLE VERIFICATION FOR HARDWARE DESIGNS AT THE REGISTER TRANSFER LEVEL  
A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting...
US20120249182 Power Routing in Standard Cell Designs  
A cell-based architecture for an integrated circuit. A row of cell instances borders a first adjacent row of cell instances along a first boundary and a second adjacent row of cell instances along...
US20120066654 STABILITY-DEPENDENT SPARE CELL INSERTION  
Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value,...
US20120331431 Symbolic Switch/Linear Circuit Simulator Systems and Methods  
Interactive and real time web-based electrical circuit symbolic solvers and simulators. The invention includes an interactive and innovative graphical user interface (GUI) for creating circuit...
US20140380257 HIERARCHICAL PUSHDOWN OF CELLS AND NETS TO ANY LOGICAL DEPTH  
A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry...
US20130179849 Automated Circuit Design For Generation of Stability Constraints for Generically Defined Electronic System with Feedback  
A method is described that involves accepting a description of an electronic system having feedback. The method further includes expressing a real root of the electronic system's transfer function...
US20120317525 IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH DIGESTS  
One method implementation disclosed includes detecting matching leaf cells that are functionally identical (optionally, functionally similar) and assigning matching names for the matching leaf...
US20130187244 PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE  
Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k...
US20150089461 METHODS FOR GENERATING SCHEMATIC DIAGRAMS AND APPARATUSES USING THE SAME  
An embodiment of the invention introduces a method for generating schematic diagrams, executed by a processing unit of an apparatus, which comprises the following steps. A pin-editing interface...
US20120240087 Voltage Drop Effect On Static Timing Analysis For Multi-Phase Sequential Circuit  
In the present invention a method to address voltage drop effect in the path based timing analysis for multi-phase sequential circuit is proposed. In calculating the new delay of the gate along...
US20130339912 HIERARCHICAL DESIGN FLOW GENERATOR  
A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a...
US20120324408 System and Method for a Chip Generator  
A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like...
US20120198398 Equivalence Checking for Retimed Electronic Circuit Designs  
Techniques and technology for formally verifying a first electronic design with a second electronic design that has been synthesized from the first electronic design, wherein the synthesis process...
US20120274357 Reducing Narrow Gate Width Effects in an Integrated Circuit Design  
A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for...
US20130198701 Single Event Upset Mitigation for Electronic Design Synthesis  
Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the...
US20150234968 PIPELINE DEPTH EXPLORATION IN A REGISTER TRANSFER LEVEL DESIGN DESCRIPTION OF AN ELECTRONIC CIRCUIT  
A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any...
US20120198397 ABSTRACTION-BASED LIVELOCK/DEADLOCK CHECKING FOR HARDWARE VERIFICATION  
Some embodiments of the present invention provide systems and techniques for checking a livelock in a circuit design. During operation, the system can identify a finite state machine (FSM) in the...
US20120192131 Partial Hardening of a Software Program from a Software Implementation to a Hardware Implementation  
System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing...
US20140282308 METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION  
The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official...
US20140191816 DESIGN STRUCTURE FOR AN INDUCTOR-CAPACITOR VOLTAGE-CONTROLLED OSCILLATOR  
Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second...
US20110029942 Soft Constraints in Scheduling  
A method for implementing soft constraints in scheduling comprises receiving a description of circuit behavior. The description is un-timed. A scheduling solution is generated for use in...
US20080072206 Unrolling Hardware Design Generate Statements in a Source Window Debugger  
Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the...

Matches 1 - 50 out of 303 1 2 3 4 5 6 7 >