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US20130132806 Convolutional Turbo Code Decoding in Receiver With Iteration Termination Based on Predicted Non-Convergence  
This disclosure introduces the concept of a strategy for a Convolutional Turbo Code decoder to make a prediction with regards to the likelihood of convergence. If a failure of convergence appears...
US20140082448 LDPC Decoder With Dynamic Graph Modification  
The present inventions are related to systems and methods for an LDPC decoder with dynamic Tanner graph modification, and in particular, to a non-erasure channel LDPC decoder that implements a...
US20120290893 METHOD AND APPARATUS FOR DETECTING A PARITY ERROR IN A SEQUENCE OF DQPSK SYMBOLS OF A DIGITAL TRANSMISSION SYSTEM  
The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r1;...
US20110099446 TRANSMISSION METHOD USING PARITY PACKETS, TRANSMITTER AND REPEATER  
Problem: A packet error rate in a receiver needs to be effectively reduced. Solution to Problem: A transmitter 11 inserts error detection codes into information packets on one-to-one basis, at a...
US20110296284 Transmission apparatus and parity calculation method  
In a transmission apparatus, a first parity calculation controller calculates parity by the frame and inserts a calculation result into a next frame to a first frame sequence. A second parity...
US20110154167 OPTIMIZING RAID MIGRATION PERFORMANCE  
A method of RAID migration comprising reading first and second blocks from a first RAID array. Said first blocks are written to a second RAID array within a first write cycle. Said second blocks...
US20110029835 Systems and Methods for Quasi-Cyclic LDPC Code Production and Decoding  
Various embodiments of the present invention provide systems and methods for generating a parity check matrix used in data processing. As an example, a method for generating a parity check matrix...
US20140082449 LDPC Decoder With Variable Node Hardening  
The present inventions are related to systems and methods for an LDPC decoder with variable node hardening, and in particular, to an LDPC decoder that temporarily hardens the value of a variable...
US20130254639 PARALLEL ENCODING FOR NON-BINARY LINEAR BLOCK CODE  
An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the...
US20070113162 Error code for wireless remote control device and method  
A method and apparatus to provide error coding for remote control communications.
US20110072336 LDPC (Low Density Parity Check) coded modulation symbol decoding  
LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an...
US20120198306 METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING IN COMMUNICATION/BROADCASTING SYSTEM  
An apparatus and method are provided for transmitting and receiving in a communication/broadcasting system. The method includes generating a codeword including a first parity bit using a first...
US20120047419 TRANSMISSION SYSTEM  
A transmission system carrying out sending and receiving of OTU frames has a first transmission device carrying out the sending of an OTU frame, and a second transmission device carrying out the...
US20090024909 TURBO CODING HAVING COMBINED TURBO DE-PADDING AND RATE MATCHING DE-PADDING  
Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit...
US20070162838 Data writing apparatus and a storage system  
An LDPC encoder (304) includes a timing adjustment circuit (326) for performing timing adjustment on main data and outputting to a writing circuit (334), a parity generation circuit (328) for...
US20130007572 System And Method For Look-Aside Parity Based Raid  
Redundant storage of information is provided by distributing storage functions between a RAID controller and switching device. The switching device multi-casts writes to storage devices and to the...
US20090138750 REDUNDANT 3-WIRE COMMUNICATION SYSTEM AND METHOD  
A redundant communication system and method for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing...
US20080168338 PARITY ERROR DETECTING CIRCUIT AND METHOD  
A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs...
US20080307294 Efficient implementation to perform iterative decoding with large iteration counts  
Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture...
US20070220410 Apparatus and method for iterative decoding in a communication system  
Disclosed are an apparatus and a method for iterative decoding of a plurality of Frame Error Check (FEC) blocks included in a frame in a wireless communication system. The method includes decoding...
US20090037799 OPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOF  
An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous...
US20100064205 SELECTIVE CACHE WAY MIRRORING  
A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way...
US20080320360 CONTROL METHOD OF INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING DEVICE  
A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33)....
US20080178065 LDPC ENCODING AND DECODING OF PACKETS OF VARIABLE SIZES  
Techniques to support low density parity check (LDPC) encoding and decoding are described. In an aspect, LDPC encoding and decoding of packets of varying sizes may be supported with a set of base...
US20090044087 Data Slicer Having An Error Correction Device  
A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels...
US20090089650 CACHE FUNCTION OVERLOADING  
A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit,...
US20100037125 SYSTEM FOR PROVIDING RUNNING DIGITAL SUM CONTROL IN A PRECODED BIT STREAM  
A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity...
US20090036051 RADIO COMMUNICATION APPARATUS AND RELAY TRANSMISSION METHOD  
Provided is a relay transmission method capable of obtaining the diversity effect even when a relay station has detected an error in a relay signal when performing communication between a base...
US20080065971 Distributed block coding (DBC)  
Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity...
US20090319871 MEMORY SYSTEM WITH SEMICONDUCTOR MEMORY AND ITS DATA TRANSFER METHOD  
A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after...
US20080256183 APPARATUS, SYSTEM, AND METHOD FOR A FRONT-END, DISTRIBUTED RAID  
An apparatus, system, and method are disclosed for a front-end, distributed redundant array of independent drives (“RAID”). A storage request receiver module receives a storage request to store...
US20080022193 ERROR CORRECTION FOR DIGITAL SYSTEMS  
An interface system is provided between a source component (210) and a destination component (220) having multiple parallel lines for transmitting data or parity bits (231-234, 251-253) and one or...
US20120151306 MULTI-ANTENNA CONFIGURATION SIGNALING IN WIRELESS COMMUNICATION SYSTEM  
A wireless communication infrastructure entity including a transceiver coupled to a controller configured to generate parity bits based on an information word. The controller is also configured to...
US20080294967 Incremental Redundancy Coding System  
In packet digital communications using a two way communications medium such as wireless each received packet is subject to noise and/or interference which causes errors in some of the received...
US20130031440 CHECKSUM USING SUMS OF PERMUTATION SUB-MATRICES  
A method for encoding data bits includes computing checksum parity bits based on the data bits. A set of equations satisfied by the data bits and the checksum parity bits corresponds to a dense...
US20130185617 WIRELESS BACKHAUL COMMUNICATION  
A method for wireless backhaul communication comprising receiving, by a wireless backhaul transmitter, a data stream in a bit format and generating, by the wireless backhaul transmitter using a...
US20050193320 Methods and apparatus for improving performance of information coding schemes  
Various modifications to conventional information coding schemes that result in an improvement in one or more performance measures for a given coding scheme. Some examples are directed to improved...
US20110264989 DISPERSED STORAGE NETWORK SLICE NAME VERIFICATION  
A method begins by a processing module dispersed storage error encoding data to produce a plurality of sets of encoded data slices in accordance with dispersed storage error coding parameters. The...
US20080276146 INCOMPLETE WRITE PROTECTION FOR DISK ARRAY  
The embodiments of the invention provide methods of protecting data blocks while writing to a storage array, wherein storage units in the storage array include write logs. The data protection...
US20050149841 Channel coding/decoding apparatus and method using a parallel concatenated low density parity check code  
A parallel concatenated low density parity check (LDPC) code having a variable code rate is provided by generating, upon receiving information bits, a first component LDPC code according to the...
US20100218070 LENGTHENING LIFE OF A LIMITED LIFE MEMORY  
A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first...
US20140164885 TIME INFORMATION OBTAINING DEVICE AND RADIO-CONTROLLED TIMEPIECE  
A time information obtaining device and a radio-controlled timepiece are shown. According to one implementation, the time information obtaining device includes the following. A code identifying...
US20050235195 Apparatus and method for encoding and decoding a low density parity check code with maximum error correction and error detection capability  
An apparatus and method for decoding a Low Density Parity Check (LDPC) code having a maximum error correction capability and an error detection capability. In the apparatus, a decoder receives a...
US20100005374 Ensuring Data Consistency  
Mechanisms for ensuring data consistency in a data store are provided. The mechanisms access a parity scrub factor f and perform a check on a data group of the data store. The check on the data...
US20140068397 PARTIAL PARITY MANAGEMENT  
A partial outer parity management system generates a product code based on a partial data block write to a data block and partial outer parity generated by a previous partial data block write to...
US20100064206 ERROR DETECTION SCHEMES FOR A CACHE IN A DATA PROCESSING SYSTEM  
A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the...
US20080270876 Decoding Apparatus, Decoding Method, and Decoding Program  
A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing...
US20080244369 REGISTER READ MECHANISM  
Integrated circuits have expanded a set of custom registers and a read mechanism for control registers. One embodiment includes a circuit having a first set of registers; a second set of registers...
US20090210742 Methods, systems and media for data recovery using global parity for multiple independent RAID levels  
Implementations described herein generally provide methods, systems and media for recovering data from disk failures. One method generally includes calculating a global parity for a group of disks...
US20070157065 Self-Protection Against Non-Stationary Disturbances  
Included are embodiments for self protection. At least one embodiment includes Self-protection Unit for protecting a signal that includes a first receiving component configured to receive data,...

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