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US20110083058 TRAPPING SET BASED LDPC CODE DESIGN AND RELATED CIRCUITS, SYSTEMS, AND METHODS  
A method of generating a Tanner graph includes generating a pseudo-random parameter and selecting a subgraph within the Tanner graph to be designed, and assigning new edges to the subgraph as a...
US20110283164 CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS  
A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different...
US20090259919 FLASH MANAGEMENT USING SEPARATE MEDTADATA STORAGE  
Disclosed are techniques for flash memory management, including storing metadata and/or error correcting information separately from payload data. In various embodiments, metadata and/or error...
US20140082459 MEASURING CELL DAMAGE FOR WEAR LEVELING IN A NON-VOLATILE MEMORY  
An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the...
US20090172499 Patrol function used in flash storage controller to detect data errors  
A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and...
US20110138253 RAM LIST-DECODING OF NEAR CODEWORDS  
Certain embodiments of the present invention are efficient run-time methods for creating and updating a RAM list of dominant trapping-set profiles for use in (LDPC) list decoding. A decoded...
US20150019922 Techniques for Adaptive Moving Read References for Memory Cell Read Error Recovery  
Examples are given for generating or providing a moving read reference (MRR) table for recovering from a read error of non-volatile memory included in a storage device. In some examples,...
US20140164879 Data Recovery on Cluster Failures and ECC Enhancements with Code Word Interleaving  
Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error...
US20140164878 Data Recovery on Cluster Failures and ECC Enhancements with Code Word Interleaving  
Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error...
US20140223264 LDPC DECODER WITH A VARIABLE NODE UPDATER WHICH USES A SCALING CONSTANT  
A first message, associated with going from one of a plurality of variable nodes to one of a plurality of check nodes is computed, wherein: (1) one or more connections between the plurality of...
US20150254133 MEMORY CONTROLLER, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM, AND CONTROL METHOD THEREFOR  
There is provide a memory controller, which substitutes a substitution page for an error page in a block including a plurality of pages in a non-volatile memory and secures a substitution block to...
US20130246891 PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE  
The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as...
US20120005559 APPARATUS AND METHOD FOR MANAGING A DRAM BUFFER  
An apparatus and method for managing a dynamic random access memory (DRAM) buffer are disclosed. The DRAM buffer managing apparatus and method may generate an error correction code (ECC) for data...
US20100042901 SUPPORTING VARIABLE SECTOR SIZES IN FLASH STORAGE DEVICES  
A flash storage device comprises a plurality of data blocks, each data block comprising a plurality of data segments, a system memory, and a controller. The controller is configured to cache in...
US20140281821 TRANSIENT PARITY/REDUNDANCY  
Mass storage uses additional error correction codes. The additional codes can be stored in a storage medium (e.g., volatile solid state memory) separate from the associated data. The additional...
US20120151286 Cross-Decoding for Non-Volatile Storage  
Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space...
US20140201599 ERROR PROTECTION FOR INTEGRATED CIRCUITS IN AN INSENSITIVE DIRECTION  
A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of...
US20140075268 METHOD FOR DODGING BAD PAGE AND BAD BLOCK CAUSED BY SUDDENLY POWER OFF  
A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off...
US20090327840 REDUNDANT DATA DISTRIBUTION IN A FLASH STORAGE DEVICE  
A flash storage device comprises a plurality of channels of flash storage, a system memory, and a controller. The controller is configured to cache, in the system memory, data to be written, to...
US20090204872 Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules  
A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a...
US20120072807 ACCESSING METADATA WITH AN EXTERNAL HOST  
Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the...
US20110154163 ACCESSING METADATA WITH AN EXTERNAL HOST  
Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the...
US20090222708 ERROR CORRECTING DEVICE AND ERROR CORRECTING METHOD  
An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the...
US20150100851 ADAPTIVE EPWR (ENHANCED POST WRITE READ) SCHEDULING  
A system and method for adaptive enhanced post write reads (EPWRs) is provided. An error rate of a block of solid state memory may be determined. Foldings may be performed more times between two...
US20130339823 BAD WORDLINE/ARRAY DETECTION IN MEMORY  
A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The...
US20130339822 BAD WORDLINE/ARRAY DETECTION IN MEMORY  
A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The...
US20140281823 SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSITY PARITY CHECK DECODING  
A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller...
US20090319863 ERROR-CORRECTING SYSTEM OF SEMICONDUCTOR MEMORY, ERROR-CORRECTING METHOD, AND MEMORY SYSTEM WITH ERROR-CORRECTING SYSTEM  
An error-correcting system includes a data buffer, a generating unit, a syndrome holding unit, a parity holding unit, and a decoding unit. The data buffer is capable of holding N bits of data. The...
US20110107188 SYSTEM AND METHOD OF DECODING DATA  
A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power...
US20110296273 METHODS AND DEVICES TO REDUCE OUTER CODE FAILURE RATE VARIABILITY  
The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page...
US20090158126 EFFICIENT INTERFERENCE CANCELLATION IN ANALOG MEMORY CELL ARRAYS  
A method includes storing data in a group of analog memory cells by writing first storage values to the cells. After storing the data, second storage values are read from the cells using one or...
US20130013981 TEMPORARY MIRRORING, LOGICAL SEGREGATION, AND REDUNDANT PROGRAMMING OR ADDRESSING FOR SOLID STATE DRIVE OPERATION  
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming...
US20120317460 IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS  
Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a...
US20100050053 ERROR CONTROL IN A FLASH MEMORY DEVICE  
Flash memory devices and associated methods are described for controlling data errors in the devices through various forms of decoding, error correction, and wear concentration. To this end, a...
US20150100852 ECC METHOD FOR DOUBLE PATTERN FLASH MEMORY  
A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an...
US20150006998 MEMORY SCRUB MANAGEMENT  
A method, computer-readable storage media, and a system are provided for managing a scrub. The method may include detecting a trigger for the scrub. The trigger may be based upon a metric of a...
US20140189468 MEMORY DEVICES AND SYSTEMS CONFIGURED TO ADJUST A SIZE OF AN ECC COVERAGE AREA  
Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ECC coverage areas, and control circuitry configured to adjust a size of one or...
US20090024905 COMBINED DISTORTION ESTIMATION AND ERROR CORRECTION CODING FOR MEMORY DEVICES  
A method for operating a memory device (24) includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells (32)...
US20140189212 PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL  
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive...
US20090125790 Method and Apparatus of Automatically Selecting Error Correction Algorithms by a NAND Flash Controller  
A method and apparatus of automatically selecting an optimal ECC algorithm by NAND Flash controller to detect and correct errors to read or write data from or to a flash memory device is...
US20090241010 MEMORY SYSTEM  
A memory system includes a controller that manages data stored in the first and second storing areas. The controller determines, when a readout error occurs when the stored data in the second...
US20140143637 LOG-LIKELIHOOD RATIO (LLR) DAMPENING IN LOW-DENSITY PARITY-CHECK (LDPC) DECODERS  
Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened codeword...
US20100017684 DATA RECOVERY IN SOLID STATE MEMORY DEVICES  
Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid...
US20140245108 ECC Management for Variable Resistance Memory Cells  
A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance...
US20090044078 ECC FUNCTIONAL BLOCK PLACEMENT IN A MULTI-CHANNEL MASS STORAGE DEVICE  
A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to...
US20100070686 METHOD AND DEVICE FOR RECONFIGURATION OF RELIABILITY DATA IN FLASH EEPROM STORAGE PAGES  
A data processing system comprises a Flash memory (120) having a storage space partitioned in a plurality of storage pages (P′). Each storage page comprises a memory reliability indicator...
US20090319871 MEMORY SYSTEM WITH SEMICONDUCTOR MEMORY AND ITS DATA TRANSFER METHOD  
A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after...
US20100058146 CHIEN-SEARCH SYSTEM EMPLOYING A CLOCK-GATING SCHEME TO SAVE POWER FOR ERROR CORRECTION DECODER AND OTHER APPLICATIONS  
Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond...
US20140068382 SYSTEMS AND METHODS TO INITIATE UPDATING OF REFERENCE VOLTAGES  
In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (CEC) is at least as large as a target error correction...
US20110231738 ERROR CORRECTION DECODING APPARATUS AND ERROR CORRECTION DECODING METHOD  
According to one embodiment, an error correction decoding apparatus including a hard-decision decoding module which performs hard-decision decoding using a signal with 2 levels per bit as input...