Match Document Document Title
US20120204081 Iterative Decoder  
An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration....
US20110289382 Programmable LDPC code decoder and decoding method thereof  
A programmable LDPC (Low-Density Parity-Check) code decoder and decoding method thereof is disclosed. By combining at least one programmable switch and at least one memory unit to decode any...
US20110083058 TRAPPING SET BASED LDPC CODE DESIGN AND RELATED CIRCUITS, SYSTEMS, AND METHODS  
A method of generating a Tanner graph includes generating a pseudo-random parameter and selecting a subgraph within the Tanner graph to be designed, and assigning new edges to the subgraph as a...
US20140229795 CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS  
A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes a first ECC codec that selectively performs...
US20110283164 CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS  
A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different...
US20110264985 SERIAL CONCATENATION OF INTERLEAVED CONVOLUTIONAL CODES FORMING TURBO-LIKE CODES  
A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The...
US20140337685 DISPERSED STORAGE HAVING A PLURALITY OF SNAPSHOT PATHS AND METHODS FOR USE THEREWITH  
A directory file includes a plurality of entries, wherein an entry of the plurality of entries includes a file or directory name field, and a snapshot list field that includes a snapshot list in...
US20130339818 ERASURE CODING AND REPLICATION IN STORAGE CLUSTERS  
A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of...
US20100153819 Decoding Method and System for Low-Density Parity Check Code  
A decoding method for LDPC code includes steps of obtaining a set of parity-check matrices of a set of block codes; obtaining an identical parity-check matrix from the set of parity-check...
US20110239088 NON-REGULAR PARITY DISTRIBUTION DETECTION VIA METADATA TAG  
This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of...
US20120246543 APPARATUS AND METHOD FOR FAST TAG HIT  
A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The...
US20110055662 NESTED DISTRIBUTED STORAGE UNIT AND APPLICATIONS THEREOF  
A method for execution by a DS storage unit begins with the DS storage unit receiving an encoded slice of a plurality of encoded slices, wherein the plurality of encoded slices was generated from...
US20140164867 STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION  
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error...
US20140041027 SAFE COMMAND EXECUTION AND ERROR RECOVERY FOR STORAGE DEVICES  
Techniques for execution of commands securely within a storage device are disclosed. Integrity of a command interpreter is verified before allowing it to execute commands within the storage...
US20120233524 LOW-DENSITY PARITY CHECK CODES FOR HOLOGRAPHIC STORAGE  
Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining...
US20090106628 SAFE COMMAND EXECUTION AND ERROR RECOVERY FOR STORAGE DEVICES  
Techniques for execution of commands securely within a storage device are disclosed. Integrity of a command interpreter is verified before allowing it to execute commands within the storage...
US20130047055 ERROR CORRECTION CODE TECHNIQUES FOR MATRICES WITH INTERLEAVED CODEWORDS  
A decoding system includes a decoder, a first module and a second module. The decoder is configured to receive data read from an optical storage medium and perform a first decoding iteration and a...
US20080184094 Programming management data for NAND memories  
Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and...
US20140149823 MEMORY WITH GUARD VALUE DEPENDENT ERROR CORRECTION  
Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on guard values that correspond to...
US20120047409 SYSTEMS AND METHODS FOR GENERATING DYNAMIC SUPER BLOCKS  
Systems and methods are disclosed for generating dynamic super blocks from one or more grown bad blocks of a non-volatile memory (“NVM”). In some embodiments, a dynamic super block can be formed...
US20110289384 MEMORY SYSTEM WITH PAGE-BASED ITERATIVE DECODING STRUCTURE AND PAGE-BASED ITERATIVE DECODING METHOD THEREOF  
A method of iteratively decoding data transferred through a channel is provided. The method may include iteratively decoding each sector of 1 to N sectors of the data in continuous succession...
US20140068375 SYSTEM AND METHOD FOR COMMUNICATING WITH LOW DENSITY PARITY CHECK CODES  
The present invention provides a low density parity check (LDPC) code system and method of using such a system. A transmitted LDPC code block size may be chosen such that the minimum transmitted...
US20140337686 DISPERSED STORAGE HAVING SNAPSHOT CLONES AND METHODS FOR USE THEREWITH  
A directory file includes a plurality of entries, wherein an entry of the plurality of entries includes a file or directory name field, and a snapshot list field that includes a snapshot list. A...
US20130151927 Executing Partial Tasks in a Distributed Storage and Task Network  
A method begins by a dispersed storage (DS) processing module receiving a partial task regarding an encoded data block grouping. The method continues with the DS processing module performing the...
US20130297986 ZERO-ONE BALANCE MANAGEMENT IN A SOLID-STATE DISK CONTROLLER  
An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event...
US20130031442 Multi-Dimensional Error Definition, Error Measurement, Error Analysis, Error Function Generation, Error Information Optimization, and Error Correction for Communications Systems  
The present invention is related to multi-dimensional error definition, error measurement, error analysis, error function generation, error information optimization, and error correction for...
US20070113155 Semiconductor storage device equipped with ECC function  
A semiconductor memory device includes a memory cell array, an ECC (error correction code) circuit and a decision circuit. The ECC circuit calculates an error correction code for write data to be...
US20110271166 PIPELINE ARCHITECTURE FOR MAXIMUM A POSTERIORI (MAP) DECODERS  
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for he first sliding...
US20130205182 APPARATUS AND METHOD FOR A DUAL MODE STANDARD AND LAYERED BELIEF PROPAGATION LDPC DECODER  
An apparatus for a dual mode low density parity check (LDPC) decoder including edge random access memory (RAM), last-in-first-out/first-in-first-out (LIFO/FIFO) RAM, channel RAM, and parallel...
US20140325307 DETECTING A UTILIZATION IMBALANCE BETWEEN DISPERSED STORAGE NETWORK STORAGE UNITS  
A method begins by a processing module of a dispersed storage network (DSN) obtaining utilization information regarding a plurality of storage units of the DSN, where first and second sets of...
US20140082455 DECODING DEVICE  
A decoding device has a decoding section that has a plurality of decoding cores which decode a received packet (e.g., likelihoods generated as a result of demodulation), which will become data to...
US20140095960 FULLY PARALLEL ENCODING METHOD AND FULLY PARALLEL DECODING METHOD OF MEMORY SYSTEM  
A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator...
US20120131417 CLASSIFYING A CRITICALITY OF A SOFT ERROR AND MITIGATING THE SOFT ERROR BASED ON THE CRITICALITY  
Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A...
US20120204080 Utilization of non-systematic (207, 187) Reed-Solomon coding in mobile/hand-held digital television receivers  
Non-systematic (207, 187) Reed-Solomon codewords contain valuable information concerning the correctness of the outer convolutional coding of the serial concatenated convolutional coding, (SCCC)...
US20120030539 ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION  
Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any...
US20080098279 USING NO-REFRESH DRAM IN ERROR CORRECTING CODE ENCODER AND DECODER IMPLEMENTATIONS  
Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many...
US20100023840 ECC CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM  
A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has...
US20070266297 CONTROLLER AND STORAGE DEVICE HAVING THE SAME  
A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first...
US20130073925 ELECTRONIC DEVICE COMPRISING ERROR CORRECTION CODING DEVICE AND ELECTRONIC DEVICE COMPRISING ERROR CORRECTION DECODING DEVICE  
An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder...
US20080115039 Destination indication to aid in posted write buffer loading  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device...
US20070067698 Techniques to perform prefetching of content in connection with integrity validation value determination  
Techniques are described herein that are capable to perform a retrieval of content from a destination buffer prior to completion of determining an integrity validation value on content of a source...
US20140258809 SYSTEMS AND METHODS FOR DECODING WITH LATE RELIABILITY INFORMATION  
Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time....
US20110154163 ACCESSING METADATA WITH AN EXTERNAL HOST  
Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the...
US20080098278 Multiplier product generation based on encoded data from addressable location  
For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number,...
US20080163028 PAGE BY PAGE ECC VARIATION IN A MEMORY DEVICE  
A data structure for a memory device is provided. The device includes an array having a plurality of rows of storage elements divided into logical units composed of a plurality of data structures....
US20110296258 ERROR CORRECTING POINTERS FOR NON-VOLATILE STORAGE  
Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be...
US20130283126 ERROR DETECTION WITHIN A MEMORY  
Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one...
US20080168328 INFORMATION RECORDING MEDIUM TO WHICH EXTRA ECC IS APPLIED, AND METHOD AND APPARATUS FOR MANAGING THE INFORMATION RECORDING MEDIUM  
An information recording medium to which data extra ECC is applied, and a method and apparatus for managing the information storage medium is provided. The method includes: determining whether...
US20130139031 LOW DENSITY PARITY CHECK CODEC  
The present invention provides a low-complexity and multi-mode Low-density Parity-check (LDPC) codec, in which the decoding operations are divided into small tasks and a unified hardware is...
US20070245218 Semiconductor integrated circuit and record player  
The present invention provides a technique capable of performing a process for encoding data read from a first storing medium and writing the encoded data to a second storing medium seemingly at...