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US20130061104 IMPROVEMENTS IN BACKWARD ANALYSIS FOR DETERMINING FAULT MASKING FACTORS  
A method and a system are presented for determining the observability of faults in an electronic circuit. In the method, for each element the time periods are determined in which an occurrent...
US20130007549 Multithreaded, mixed-HDL/ESL Concurrent Fault Simulator for Large-Scale Integrated Circuit Designs  
Techniques for performing multiprocessing/multithreaded concurrent fault simulation of large-scale integrated circuit (IC) designs are described herein. Specifically, an IC design's source files,...
US20060095824 Determining circuit behavior  
Systems, methodologies, media, and other embodiments associated with automatically determining circuit behavior are described. One exemplary system embodiment includes a data acquisition logic...
US20050149806 Failure detection simulation system  
A failure detection simulation system has a storage unit and a simulation unit. The storage unit stores a failure model parameter indicative of a characteristic of a failure status of a circuit...
US20120216091 Method of Analyzing the Safety of a Device Employing On Target Hardware Description Language Based Fault Injection  
A method of testing a target electronic device implemented in a configurable integrated circuit device includes receiving a baseline design for the target electronic device in a hardware...
US20080115028 METHOD AND SYSTEM FOR TEST VERIFICATION OF INTEGRATED CIRCUIT DESIGNS  
A method and system for verifying the design of an integrated circuit including an analog portion and a digital portion are disclosed. As one example, a method for verifying the design of an...
US20090031181 Automated root cause identification of logic controller failure  
A method, system, and computer program product for automated root cause identification of a failure of a logic controller have been provided. The method includes receiving logic controller failure...
US20060195744 Method and apparatus to simulate automatic test equipment  
A virtual tester that simulates automatic test equipment (ATE). A translator converts program code of the ATE to pattern information and timing information. The virtual tester tests a software...
US20060230326 Method for re-using test cases through standardization and modularity  
A method is disclosed for creating test cases for simulating the design and operation of an integrated circuit having operational functionality that requires adherence to a multiplicity of...
US20060156140 Network equipment and a method for monitoring the start up of such an equipment  
The invention concerns a network equipment for connection to a local network and a method for monitoring the start up of a such an equipment. This equipment comprises a persistent memory for...
US20050166115 Method for performing software stress test  
Described is a method for generating a usage task from usage data, constructing a pattern graph from the usage task, constructing a model graph which represents a space of equivalents to the usage...
US20120151290 GRAPH MATCHING SYSTEM FOR COMPARING AND MERGING FAULT MODELS  
A method and system for comparing and merging fault models which are derived from different data sources. Two or more fault models are first represented as bipartite weighted graphs, which define...
US20080086668 MODEL-BASED TESTING METHOD AND SYSTEM USING EMBEDDED MODELS  
A testing system and various methods involving testing of a device under test (DUT) use a device model to model a stimulus-response behavior of a the DUT. The testing system includes a device...
US20080040637 DIAGNOSING MIXED SCAN CHAIN AND SYSTEM LOGIC DEFECTS  
Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system...
US20080052586 Low power decompression of test cubes  
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be...
US20140143625 COMPUTER-READABLE RECORDING MEDIUM, FAILURE PREDICTION DEVICE AND APPLICABILITY DETERMINATION METHOD  
A failure prediction device generates a failure predictor pattern in accordance with previous cases of failure that has occurred in a first system, the failure predictor pattern being used to...
US20060253760 System and methods for processing software authorization and error feedback  
Software error feedback information, typically that associated with authorization failures due to operating system resource access checks, is automatically communicated to a software vendor with...
US20070226570 SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES  
Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of...
US20060179385 Context-sensitive user help in a software-based development environment  
The invention relates to a method, a system and a computer program product for provision of user information within a software-based development environment for designing circuits and/or systems...
US20060184850 Apparatus for preventing bus reset when removing a device from an IEEE 1394 network  
Disclosed is an apparatus for preventing bus reset when a node is removed in an Institute of Electrical and Electronics Engineers (IEEE) 1394 network. The apparatus includes a tone signal...
US20100138710 LOGIC VERIFICATION APPARATUS  
To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A...
US20050204241 Method and device for analyzing software error  
In a cause categorization step, bugs are categorized according to technical causes. In a damage evaluation step, how many steps the process has turned back due to a bug is measured. In a damage...
US20050138515 Method and apparatus for co-verification of digital designs  
A method and apparatus for development and concurrent verification of digital designs including a combination of a microprocessor and discrete logic design blocks. The hardware/software design...
US20060200721 Tester simulation system and tester simulation method using same  
It is an object of the invention to implement a tester simulation system capable of finding margins of respective expected value determining timings in a short time, and a tester simulation method...
US20070022349 Test apparatus with tester channel availability identification  
Automated semiconductor device tester apparatus includes a plurality of tester channels for devices under test. The apparatus includes an automated switching module, for switching an unused...
US20080244347 Automated Circuit Model Generator  
A method, system and program reduce ATPG processing times by eliminating non-value added cells in a circuit model that that is provided to an ATPG system. The elimination of non-value added cells...
US20050086565 System and method for generating a test case  
A system and method for generating a test case operable to test a circuit design using a plurality of threads. In one embodiment, a test code and state initialization engine, responsive to a...
US20110078526 Method and Circuit Configuration for Simulating Fault States in a Control Unit  
A method and a circuit configuration for simulating fault states in a control unit, as well as a computer program and a computer-program product, are provided. In this context, a multiplexer and a...
US20070220390 Method and system for verifying equivalence of two representations of a stimulus pattern for testing a design  
A method for verifying the equivalence of two representations of a stimulus pattern for testing a design is disclosed. The method includes receiving a base pattern file representing the stimulus...
US20100286797 METHOD AND SYSTEM FOR TESTING SAFETY AUTOMATION LOGIC OF A MANUFACTURING CELL  
A method for testing the safety automation logic used in a manufacturing cell includes recording control signals of a safety-related component such as an E-Stop, light curtain, gate lock, or a...
US20090077441 METHOD AND APPARATUS FOR SCHEDULING TEST VECTORS IN A MULTIPLE CORE INTEGRATED CIRCUIT  
A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first...
US20090083600 Systems and methods for critical node filtering of integrated circuits  
Systems, apparatuses, methods, and computer program products for performing silicon debugging and isolating faults in integrated circuits are disclosed. Some embodiments comprise a simulator to...
US20090287974 Method of generating test condition for detecting delay faults in semiconductor integrated circuit and apparatus for generating the same  
Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment,...
US20100122132 METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC AND TRIGGER LOGIC  
A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger...
US20060020866 System and method for monitoring performance of network infrastructure and applications by automatically identifying system variables or components constructed from such variables that dominate variance of performance  
Systems, methods and computer program products for monitoring performance of network infrastructure and applications by automatically identifying system variables or combinations constructed from...
US20070288822 Timing-aware test generation and fault simulation  
Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test...
US20100064191 DIAGNOSTIC DEVICE, DIAGNOSTIC METHOD, PROGRAM, AND RECORDING MEDIUM  
Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic device 1 has a symbol injection part 3, which is...
US20110289373 Electornic Design Emulation Display Tool  
One or more technologies described herein can be used for viewing results of a simulation of a software executable in a multi-processor electronic circuit design. A debug environment can display...
US20090164861 METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH  
A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction...
US20050268195 Apparatus and method for improving emulation speed of high-level languages in on-chip emulation systems  
Methods and apparatus for stepping-over and stepping-out of functions encountered during program execution on a target processor during debug operations are implemented within a combination of an...
US20070245197 Method and apparatus for identifying paths having appropriate lengths for fault simulation  
A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate...
US20160320451 SIMULATION VERIFICATION METHOD FOR FPGA FUNCTION MODULES AND SYSTEM THEREOF  
A simulation verification method for Field Programmable Gate Array (FPGA) function modules and a system thereof. The method includes: generating all test cases by enumerating all parameter...
US20160209469 SCHEDULING OF SCENARIO MODELS FOR EXECUTION WITHIN DIFFERENT COMPUTER THREADS AND SCHEDULING OF MEMORY REGIONS FOR USE WITH THE SCENARIO MODELS  
A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a...
Matches 1 - 43 out of 43