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US20110055650 Hold Transition Fault Model and Test Generation Method  
A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold...
US20080222472 METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME  
A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the...
US20120297264 Root Cause Distribution Determination Based On Layout Aware Scan Diagnosis Results  
Aspects of the invention relate to yield analysis techniques for generating root cause distribution information. Suspect information for a plurality of failing dies is first generated using a...
US20080222473 TEST PATTERN GENERATING DEVICE AND TEST PATTERN GENERATING METHOD  
An apparatus for LSI test has a risk place extraction unit supplied with a design information of the LSI to specify a place by estimating an error in LSI operation based on the design information...
US20080034266 Tester For Testing Semiconductor Device  
A tester for testing a semiconductor device is disclosed. The tester for testing the semiconductor device employs a data selector for converting a logical test pattern data transmitted from a...
US20140344637 SEQUENTIAL LOGIC SENSITIZATION FROM STRUCTURAL DESCRIPTION  
A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a...
US20110022910 ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM  
An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive...
US20100100786 SERIAL TEST MODE OF AN INTEGRATED CIRCUIT (IC)  
A methodology to perform testing of integrated circuits (IC) wherein a reduced number of Input/Output (IO) pins may used to load testing patterns and capture test results from test structures...
US20090024893 INTEGRATED CIRCUIT ARRANGEMENT AND DESIGN METHOD  
An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being...
US20080263423 System and Method for Nonlinear Statistical Encoding in Test Data Compression  
A method for test data compression includes generating a plurality of test cubes, each test cube comprising test cube data. Each test cube is compared with at least one other test cube, as test...
US20070234166 Inverter and display device having the same  
A display device and an inverter therefor are disclosed. The inverter has a main circuit board having a plurality of first circuit patterns and a plurality of second circuit patterns formed on a...
US20080195906 TEST PATTERN GENERATION APPARATUS AND TEST PATTERN GENERATION METHOD  
A test pattern generation apparatus extracts processing that coincides with input combinational test confirmation processing from program test patterns stored in a file, extracts execution...
US20060236185 Multiple function results using single pattern and method  
A testing system for testing a manufactured semiconductor component includes a main processor and a pattern generator. The main processor is configured to run a main program. The pattern generator...
US20150234007 GENERATION DEVICE, GENERATION METHOD, AND PROGRAM  
Provided is a generation device including: a test vector generation unit for selecting, for each of parameters to be included in a test vector, one value from among possible values for the...
US20070089010 Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device  
A test apparatus for testing digitized test responses has a generator (2) and a signal extractor (3). The generator (2) uses direct digital synthesis to generate a set of n digital reference...
US20060200720 Generating and verifying read and write cycles in a PCI bus system  
A peripheral device to generate read and write cycles on a PCI bus comprises a PCI bus interface. A control unit has a data pattern generator to source a data pattern to a target via the interface...
US20070260954 Integrated circuit with low-power built-in self-test logic  
An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern...
US20060026479 Verification vector creating method, and electronic circuit verifying method using the former method  
To realize an equivalence verification between an analog circuit and its function model unit. From a circuit topology and a functional description, there is extracted contained in the circuit. A...
US20090282307 Optimizing test code generation for verification environment  
A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target...
US20080052586 Low power decompression of test cubes  
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be...
US20090183045 TESTING SYSTEM FOR A DEVICE UNDER TEST  
A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so...
US20080098271 System and Method for Verification and Generation of Timing Exceptions  
The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second...
US20110185311 MOTION ENABLED MULTI-FRAME CHALLENGE-RESPONSE TEST  
A method for generating a multi-frame image rendering of a challenge-response test on a display is presented. The method begins by identifying a pattern with graphical elements, and a display...
US20070104085 VARYING SCRAMBLING/OVSF CODES WITHIN A TD-CDMA SLOT TO OVERCOME JAMMING EFFECT BY A DOMINANT INTERFERER  
Scrambling/OVSF codes are varied with a TD-CDMA slot to overcome jamming effects by a dominant interferer. Interference is detected and a scrambling code sequence is varied and employed to...
US20080270865 Vendor Independent Method to Merge Coverage Results for Different Designs  
A method, computer program product, and data processing system for combining results regarding test sequences' coverage of events in testing a plurality of related semiconductor designs are...
US20070300115 APPARATUS AND METHOD FOR ACCELERATING TEST, DEBUG AND FAILURE ANALYSIS OF A MULTIPROCESSOR DEVICE  
An apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device are provided. With the apparatus and method, on-chip trace logic is utilized to receive...
US20060041808 Test-pattern generation system, test-pattern analysis system, test-pattern generation method, test-pattern analysis method, and computer product  
An activation test sequence: 11XX0 with a test sequence ID: 8 is input to an ATPG to generate an activation test sequence: 11000. A propagation test sequence: 11XX1 with a test sequence ID: 8 is...
US20080141089 Semiconductor Integrated Circuit and System Lsi  
In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal 104...
US20080082886 Sub-instruction repeats for algorithmic pattern generators  
An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with...
US20080072112 Sequential Scan Technique Providing Reliable Testing of an Integrated Circuit  
Determining a scan vector which would test an integrated circuit (IC) while ensuring counts in respective portions of the IC would not exceed corresponding thresholds. In an embodiment, the...
US20140089752 METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER CIRCUITRY  
Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a...
US20090006917 TEST CIRCUIT FOR SUPPORTING CONCURRENT TEST MODE IN A SEMICONDUCTOR MEMORY  
A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving...
US20100095179 TEST PATTERN GENERATION METHOD FOR AVOIDING FALSE TESTING IN TWO-PATTERN TESTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT  
A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test...
US20070162807 High-speed serial transfer device test method, program, and device  
A test pattern generating unit generates a test pattern in which unconverted data is arranged such that same values of 0 or 1 bits in converted data according to a code conversion table are...
US20070136631 Method and system for testing backplanes utilizing a boundary scan protocol  
A system is provided for testing connectivity of a backplane having card slots with multiple nets in each card slot. The system includes a processor module that generates test vectors based on a...
US20150180618 ONLINE DESIGN VALIDATION FOR ELECTRONIC DEVICES  
A computer implemented process is described for testing multiple electronic devices under test (DUTs). A design test pattern or command/instruction is generated with an electronic design...
US20070300116 ASYNCHRONOUS SET-RESET CIRCUIT DEVICE  
An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool may include a pair of logic gates having at least two inputs each, and a logic...
US20080189585 SEMICONDUCTOR TESTING SYSTEM  
There is provided a semiconductor testing system capable of achieving a higher speed in transmission of signals while holding back an increase in the number of transmission paths, and preventing...
US20100058131 TEST APPARATUS, TEST VECTOR GENERATE UNIT, TEST METHOD, PROGRAM, AND RECORDING MEDIUM  
Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a vector selecting section that selects...
US20090013230 CIRCUIT ARRANGEMENT AND METHOD OF TESTING AND/OR DIAGNOSING THE SAME  
To further develop a circuit arrangement (100; 100′), and in particular an application circuit, that is arranged to generate at least one test pattern, and a method of testing and/or diagnosing...
US20070033473 LSI inspection module, control method for LSI inspection module, communication method between LSI inspection module and inspection apparatus, and LSI inspection method  
In an LSI inspection module, an I/O interface compatible with the I/O interface of an LSI as an inspection target is provided and testing data is stored in a memory for test data. During...
US20100146350 TEST GENERATION METHODS FOR REDUCING POWER DISSIPATION AND SUPPLY CURRENTS  
Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for...
US20050044463 Programmable jitter generator  
A jitter generator produces a jittery test signal for use in performing a jitter test on an integrated circuit (IC) device under test (DUT). The jitter generator includes a programmable delay...
US20120089879 METHOD AND SYSTEM FOR IDENTIFYING POWER DEFECTS USING TEST PATTERN SWITCHING ACTIVITY  
A method and system for identifying power defects using test pattern switching activity is disclosed. In one embodiment, a plurality of test patterns is applied to a circuit under test, and...
US20090319842 GENERATING DEVICE, GENERATING METHOD, PROGRAM AND RECORDING MEDIUM  
Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation device 100 generates a test vector for a logic circuit by...
US20090271677 Data Transformation Method and Related Device for a Testing System  
A data transformation method for a testing system includes receiving a test signal comprising a test data and a timing information corresponding to the test data, and transforming the test data...
US20090265597 SIGNAL OUTPUT DEVICE, SIGNAL DETECTION DEVICE, TESTER, ELECTRON DEVICE, AND PROGRAM  
There is provided a signal output apparatus for outputting a pattern signal. The signal output apparatus includes a pattern generating section that generates waveform data of the pattern signal to...
US20100223519 COMPACT JTAG ADAPTER  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20060265632 Chip capable of testing itself and testing method thereof  
A chip capable of testing itself and a testing method thereof. The chip capable of testing itself is electrically connected to a processor. The chip tests itself with a testing mode. The chip...
US20110138242 METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES  
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear...

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