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US20120324302 |
INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE
An integrated circuit configured for testing is described. The integrated circuit includes a high-speed input/output interface. The integrated circuit also includes a test controller coupled to... |
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US20060259840 |
SELF-TEST CIRCUITRY TO DETERMINE MINIMUM OPERATING VOLTAGE
A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for... |
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US20050289424 |
Error correction in ROM embedded DRAM
Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access... |
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US20050039098 |
Apparatus and method for self testing programmable logic arrays
A self-testing programmable logic array PLA system has an array of programmably interconnected logic cells, a built-in self-test (BIST) structure interconnected with the logic cells, and a BIST... |
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US20090006916 |
METHOD FOR CACHE CORRECTION USING FUNCTIONAL TESTS TRANSLATED TO FUSE REPAIR
A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory,... |
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US20140229782 |
Automatic Test Equipment
Embodiments of the present invention provide an automatic test equipment. The automatic test equipment is configured to receive an input signal from a device under test and to write an information... |
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US20120324305 |
TESTING INTERPOSER METHOD AND APPARATUS
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the... |
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US20050289423 |
Built-in self test systems and methods for multiple memories
A built-in self-test architecture for multiple memories in a chip is proposes in the present invention. In this architecture, a memory testing circuit includes a data generator for generating... |
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US20170023645 |
SEMICONDUCTOR DEVICE
A semiconductor device in which the area of a circuit that is unnecessary during normal operation is small. The semiconductor device includes a first circuit and a second circuit. The first... |
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US20100293426 |
SYSTEMS AND METHODS FOR A PHASE LOCKED LOOP BUILT IN SELF TEST
An apparatus configured for a phase locked loop (PLL) built in self test (BIST) jitter measurement is described. The apparatus includes a phase detector. The phase detector produces a digital... |
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US20050102594 |
Method for test application and test content generation for AC faults in integrated circuits
A method for generating a software-based self-test in an integrated circuit includes extracting constraints for corresponding instructions for the integrated circuit, modeling the constraints for... |
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US20080016421 |
METHOD AND APPARATUS FOR PROVIDING PROGRAMMABLE CONTROL OF BUILT-IN SELF TEST
A method and apparatus provides programmable control of built-in self test. A programmable controller allows software selectively to run BIST on different ports of the complex circuit and examine... |
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US20070011535 |
Semiconductor integrated circuit
A semiconductor integrated circuit includes a plurality of memories; a BIST circuit configured to test at least one of the memories; and a plurality of shift circuits connected to each of the... |
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US20090089636 |
Method and Apparatus for Logic Built In Self Test (LBIST) Fault Detection in Multi-Core Processors
A method, system, and computer program product for identifying failures in multi-core processors, utilizing logic built-in self test (LBIST) technology. Multi-core processors, having LBIST and... |
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US20080082884 |
TEST CONTROL CIRCUIT
In a conventional semiconductor device, to effectively improve a toggling coefficient of a memory circuit, a test pattern and the like must be inputted from the outside, and there has been a... |
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US20060179378 |
Semiconductor integrated circuit and method of testing the same
In this semiconductor integrated circuit, outputs of a fuse for power supply level adjustment and an internal register are selectively switched by a selector, and a selected output is inputted to... |
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US20080195901 |
OP-CODE BASED BUILT-IN-SELF-TEST
A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a... |
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US20050251714 |
Test apparatus for semiconductor devices built-in self-test function
A test apparatus for semiconductor devices comprises a self-test circuit carried on the semiconductor device and for test the semiconductor device. A tester supplies data signals, clock signals,... |
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US20100275076 |
SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME
A semiconductor integrated circuit includes: a memory; a logic circuit configured to output an address signal for an address of the memory; and an address control circuit connected with the logic... |
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US20070283204 |
METHOD AND SYSTEM FOR DETERMINISTIC BIST
Methods, systems and articles of manufactures are provided for built-in self-testing of high-performance circuits configured to generate and apply test patterns to a circuit under test (CUT). A... |
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US20070011537 |
Systems and methods for self-diagnosing LBIST
Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits. In one embodiment, a system has first and second target logic, each of which has LBIST circuitry... |
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US20080109691 |
Method and Apparatus for Executing a BIST Routine
During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The... |
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US20110099443 |
TEST APPARATUS
Provided is a test apparatus that tests a device under test, comprising a plurality of test circuits that each perform a predetermined test function; a plurality of I/O circuits that are provided... |
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US20090144595 |
BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS
A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a... |
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US20080155363 |
BIST CIRCUIT DEVICE AND SELF TEST METHOD THEREOF
A BIST circuit device includes a test memory, a test result storage memory having the capacity equal to or larger than the capacity of the test memory, and a control circuit which performs a test... |
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US20080077835 |
Automatic Test Equipment Receiving Diagnostic Information from Devices with Built-in Self Test
Automatic test equipment capable of receiving diagnostic information from a device under test having a built-in self-test system (BIST) and a diagnostic information collector in which the... |
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US20070168809 |
Systems and methods for LBIST testing using commonly controlled LBIST satellites
Systems and methods for performing logic built-in self-tests (LBISTs) in which an LBIST controller provides control signals to multiple LBIST satellites that are co-located with different... |
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US20150106673 |
METHOD AND APPARATUS FOR ON-THE-FLY MEMORY CHANNEL BUILT-IN-SELF-TEST
The present invention discloses a memory channel bridge with a BIST module; and the memory channel bridge interfaces other channels in a SOC to access a memory module. During a DFT test, SOC... |
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US20090300448 |
SCAN FLIP-FLOP DEVICE
A scan flip-flop device has a scan flip-flop, a Nch insulated gate field effect transistor and a Pch insulated gate field effect transistor. The Nch insulated gate field effect transistor is... |
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US20090228751 |
METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICONDUCTOR CHIP AND A CORRESPONDING SEMICONDUCTOR CHIP WITH A TEST ENGINE
A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements... |
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US20060156132 |
Semiconductor device with built-in scan test circuit
The clock cycle during the shift operation is set shorter than the clock cycle during the capture operation in the scan test circuit. For example, the clock cycle during the shift operation is set... |
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US20110029827 |
METHOD, APPARATUS, AND DESIGN STRUCTURE FOR BUILT-IN SELF-TEST
In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in... |
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US20070061654 |
Semiconductor integrated circuit and test method
A semiconductor integrated circuit includes a memory that operates in synchronization with a first clock and a built-in self-test (BIST) circuit for testing the memory. The BIST circuit includes a... |
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US20060212768 |
Verification circuitry for master-slave system
Operation of a system including master and slave devices is verified through the use of system verification circuitry including a test master circuit that outputs test patterns on the system bus... |
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US20070266349 |
DIRECTED RANDOM VERIFICATION
A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested... |
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US20060053356 |
Integrated circuit
An integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a parallel access memory BIST circuit. The first scan... |
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US20060041807 |
Integrated circuit
An integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a serial access memory BIST circuit. The first scan... |
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US20100318865 |
SIGNAL PROCESSING APPARATUS INCLUDING BUILT-IN SELF TEST DEVICE AND METHOD FOR TESTING THEREBY
A signal processing apparatus according to the present invention includes: a built-in self test device dividing a digital reference clock signal to output an I division signal and a Q division... |
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US20080077836 |
Diagnostic Information Capture from Memory Devices with Built-in Self Test
From a memory device comprising a built-in self-test system (BIST), diagnostic information is obtained by using the BIST to write a test pattern at a memory location in the memory device and to... |
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US20080256405 |
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS
A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at... |
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US20130179745 |
TEST INTERFACE CIRCUIT FOR INCREASING TESTING SPEED
A test interface circuit couplable between a source driver and test equipment is disclosed. The test interface circuit includes a plurality of test interface modules and a logic circuit. Each of... |
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US20100107026 |
Semiconductor device having built-in self-test circuit and method of testing the same
A semiconductor device includes circuits to be tested, an input terminal for receiving a tester clock signal from outside, a built-in self-test (BIST) circuit for logically testing the circuit at... |
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US20120124440 |
LBIST DIAGNOSTIC SCHEME
A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility... |
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US20080046789 |
APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INTEGRATED CIRCUITS
This patent describes a method for varying the amplitude and frequency of power supply oscillations produced by content addressable memories or other critical circuits using BIST. Supply... |
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US20080098269 |
Mechanism for concurrent testing of multiple embedded arrays
In one embodiment, an apparatus and method for concurrent testing of multiple embedded arrays is disclosed. In one embodiment, the apparatus comprises a built-in self test (BIST) engine coupled to... |
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US20070226567 |
HIGH SPEED BIST UTILIZING CLOCK MULTIPLICATION
A system and method of performing high speed built-in self test (BIST) using clock multiplication. A system is provided for testing a high speed integrated circuit using a low speed tester,... |
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US20090063921 |
Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration
A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in... |
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US20080086781 |
METHOD AND SYSTEM FOR GLITCH PROTECTION IN A SECURE SYSTEM
Aspects of a method and system for glitch protection in a secure system are provided. In this regard, the output of an on-chip security operation may be combinatorially compared with an expected... |
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US20160282408 |
Integrated Circuit Including a Programmable Logic Analyzer with Enhanced and Debugging Capabilities and a Method Therefor
A system including an embedded logic analyzer block having an input receiving a plurality of signals from a system under test, and a trigger event block detecting an occurrence of an event based... |
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US20070033471 |
Hardware Configuration of pBIST
This invention is a method of constructing an integrated circuit with built-in self test. The built-in self test includes a built-in self test unit a read only memory storing test algorithms and... |