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US20110209021 Failure Detection and Mitigation in Logic Circuits  
The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected...
US20070266349 DIRECTED RANDOM VERIFICATION  
A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested...
US20110264972 SELF-DIAGNOSIS SYSTEM AND TEST CIRCUIT DETERMINATION METHOD  
Provided are a self-diagnosis system and a test circuit determination method that are capable of determining normality of a test circuit which diagnoses a test target circuit. A self-diagnosis...
US20150169423 DESIGN-BASED WEIGHTING FOR LOGIC BUILT-IN SELF-TEST  
Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer...
US20150168489 DESIGN-BASED WEIGHTING FOR LOGIC BUILT-IN SELF-TEST  
Embodiments relate to design-based weighting for logic built-in self-test (LBIST). An aspect includes a computer program product for implementing design-based weighting for LBIST. The computer...
US20150153409 CIRCUIT FOR TESTING POWER SUPPLIES IN MULTIPLE POWER MODES  
A BIST circuit is provided for testing the status of power supplies in an integrated circuit in multiple power modes including multiple circuit blocks. The BIST circuit includes a finite state...
US20100088563 SAVING DEBUGGING CONTEXTS WITH PERIODIC BUILT-IN SELF-TEST EXECUTION  
A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic...
US20150039957 DYNAMIC BUILT-IN SELF-TEST SYSTEM  
A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The...
US20140013177 ON-CHIP FUNCTIONAL DEBUGGER AND A METHOD OF PROVIDING ON-CHIP FUNCTIONAL DEBUGGING  
An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the...
US20110161760 ON-CHIP FUNCTIONAL DEBUGGER AND A METHOD OF PROVIDING ON-CHIP FUNCTIONAL DEBUGGING  
An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the...
US20060156132 Semiconductor device with built-in scan test circuit  
The clock cycle during the shift operation is set shorter than the clock cycle during the capture operation in the scan test circuit. For example, the clock cycle during the shift operation is set...
US20080092003 Diagnostic Information Capture from Logic Devices with Built-in Self Test  
From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector...
US20120030533 IMPLEMENTING SWITCHING FACTOR REDUCTION IN LBIST  
A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides....
US20080072111 Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit  
The present invention relates to a method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected...
US20100318863 PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES  
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access...
US20060212768 Verification circuitry for master-slave system  
Operation of a system including master and slave devices is verified through the use of system verification circuitry including a test master circuit that outputs test patterns on the system bus...
US20090254788 Techniques for Logic Built-In Self-Test Diagnostics of Integrated Circuit Devices  
A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC...
US20100318866 TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT  
The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and...
US20070226567 HIGH SPEED BIST UTILIZING CLOCK MULTIPLICATION  
A system and method of performing high speed built-in self test (BIST) using clock multiplication. A system is provided for testing a high speed integrated circuit using a low speed tester,...
US20090300446 Selective Per-Cycle Masking Of Scan Chains For System Level Test  
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence...
US20150100842 BUFFER TESTING FOR RECONFIGURABLE INSTRUCTION CELL ARRAYS  
A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar...
US20070260954 Integrated circuit with low-power built-in self-test logic  
An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern...
US20100050031 Providing Pseudo-Randomized Static Values During LBIST Transition Tests  
An LBIST captures pseudo-random values from a pseudo-random pattern generator. Next, the LBIST stabilizes an untimed logic path by inputting the captured pseudo-random value into the untimed logic...
US20110161761 PROBELESS TESTING OF PAD BUFFERS ON WAFER  
The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.
US20140189456 3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION  
Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described...
US20090113264 BUILT IN SELF TEST FOR INPUT/OUTPUT CHARACTERIZATION  
A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the...
US20090217115 Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy  
A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited...
US20120084614 SERIAL SCAN CHAIN IN A STAR CONFIGURATION  
A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase...
US20120324302 INTEGRATED CIRCUIT FOR TESTING USING A HIGH-SPEED INPUT/OUTPUT INTERFACE  
An integrated circuit configured for testing is described. The integrated circuit includes a high-speed input/output interface. The integrated circuit also includes a test controller coupled to...
US20090172487 Multiple pBIST Controllers  
A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to...
US20140129888 STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES  
Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A...
US20080082884 TEST CONTROL CIRCUIT  
In a conventional semiconductor device, to effectively improve a toggling coefficient of a memory circuit, a test pattern and the like must be inputted from the outside, and there has been a...
US20110099443 TEST APPARATUS  
Provided is a test apparatus that tests a device under test, comprising a plurality of test circuits that each perform a predetermined test function; a plurality of I/O circuits that are provided...
US20120266037 TAP TIME DIVISION MULTIPLEXING WITH SCAN TEST  
An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a...
US20080141089 Semiconductor Integrated Circuit and System Lsi  
In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal 104...
US20070118784 SELF TEST CIRCUIT FOR A SEMICONDUCTOR INTERGRATED CIRCUIT  
A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock...
US20060156131 Method of reducing hardware overhead upon generation of test pattern in built-in sef test  
A method of reducing hardware overhead upon the generation of a test pattern in a built-in self test is introduced, in which two pieces of hardware perform a lot of functions even prior to...
US20090132883 TEST CIRCUIT  
A test circuit includes a plurality of circuit blocks having a same circuit construction and a same function, a plurality of internal test circuits each corresponding to a different one of the...
US20080209293 PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICES  
A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system...
US20130139017 1149.1 TAP LINKING MODULES  
IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry...
US20120096325 In or relating to 1149.1tap linking modules  
Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs...
US20080195901 OP-CODE BASED BUILT-IN-SELF-TEST  
A built-in-self-test (BIST) system for testing a memory that includes a scheduler module that generates a first test algorithm based on a set of operational codes. Each operational code defines a...
US20110167311 System and Method for Analyzing an Electronics Device Including a Logic Analyzer  
A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic...
US20090144595 BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS  
A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a...
US20140281778 BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL  
A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first...
US20130191695 IMPLEMENTING ENHANCED PSEUDO RANDOM PATTERN GENERATORS WITH HIERARCHICAL LINEAR FEEDBACK SHIFT REGISTERS (LFSRs)  
A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random...
US20100223519 COMPACT JTAG ADAPTER  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20140331099 INTEGRATED CIRCUIT WITH TOGGLE SUPPRESSION LOGIC  
An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable...
US20080077836 Diagnostic Information Capture from Memory Devices with Built-in Self Test  
From a memory device comprising a built-in self-test system (BIST), diagnostic information is obtained by using the BIST to write a test pattern at a memory location in the memory device and to...
US20120221910 MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)  
Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical...

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