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US20150177327 In Situ on the Fly On-Chip Variation Measurement  
A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated...
US20130103997 IEEE1588 PROTOCOL NEGATIVE TESTING METHOD  
The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback...
US20110161759 SCAN ARCHITECTURE AND DESIGN METHODOLOGY YIELDING SIGNIFICANT REDUCTION IN SCAN AREA AND POWER OVERHEAD  
A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality...
US20140101505 CLOCK CONTROL FOR REDUCING TIMING EXCEPTIONS IN SCAN TESTING OF AN INTEGRATED CIRCUIT  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality...
US20120124439 Wrapper Cell for Hierarchical System on Chip Testing  
Wrapper cells for simultaneous testing of parent functional elements and child functional elements in a hierarchical SoC (System on Chip) provide a substantially reduced integrated circuit...
US20140189455 SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE GLOBAL LEVEL FOR SCAN BASED TESTS  
A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree....
US20120072797 DESIGN-FOR-TEST TECHNIQUE TO REDUCE TEST VOLUME INCLUDING A CLOCK GATE CONTROLLER  
Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry...
US20080010573 Test clock control structures to generate configurable test clocks for scan-based testing of electronic circuits using programmable test clock controllers  
Systems, structures and methods for generating a test clock for scan chains to implement scan-based testing of electronic circuits are disclosed. In one embodiment, a test clock control structure...
US20110078525 Method and Apparatus of ATE IC Scan Test Using FPGA-Based System  
An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs),...
US20120030532 STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING  
A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of...
US20110099442 ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS  
A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can...
US20110072326 SRAM MACRO TEST FLOP  
A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch...
US20060225010 Semiconductor device and scan test method  
A semiconductor device includes a clock signal separating circuit and a logic circuit. The clock signal separating circuit separates a clock signal into a first separation clock signal and a...
US20110296265 SYSTEM FOR TESTING INTEGRATED CIRCUIT WITH ASYNCHRONOUS CLOCK DOMAINS  
A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal...
US20150226801 Functional Testing of an Integrated Circuit Chip  
A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising...
US20110107072 METHOD FOR SELF-DIAGNOSING SYSTEM MANAGEMENT INTERRUPT HANDLER  
A method for self-diagnosing a system management interrupt (SMI) handler is provided. A first time value is obtained from an advanced configuration and power interface (ACPI) timer at a time of...
US20080010572 Scan-based testing of devices implementing a test clock control structure ("TCCS")  
Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed. In one embodiment, a method includes performing an...
US20120233513 METHOD FOR CREATING TEST CLOCK DOMAIN DURING INTEGRATED CIRCUIT DESIGN, AND ASSOCIATED COMPUTER READABLE MEDIUM  
In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan...
US20140075257 Computer-Aided Design (CAD) Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults  
A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test...
US20120079334 Low Power Scannable Latch  
A scannable latch circuit is disclosed. In one embodiment, the scannable latch circuit includes a master latch, a slave latch, and a gating circuit coupled between the master latch and the slave...
US20120173943 APPARATUS FOR AT-SPEED TESTING, IN INTER-DOMAIN MODE, OF A MULTI-CLOCK-DOMAIN DIGITAL INTEGRATED CIRCUIT ACCORDING TO BIST OR SCAN TECHNIQUES  
An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions...
US20090119561 Microcomputer and Method of Testing The Same  
Embodiments of the present invention provide a microcomputer on which a plurality of ICs (Integrated Circuits) connected from one another by a source-synchronous interface is mounted. The...
US20090125770 SCAN BASED COMPUTATION OF A SIGNATURE CONCURRENTLY WITH FUNCTIONAL OPERATION  
A method and circuit for capturing and observing the internal state of an integrated circuit that utilizes a scan chain capable of capturing the functional state of an integrated circuit during...
US20090132879 MULTIPLEXING OF SCAN INPUTS AND SCAN OUTPUTS ON TEST PINS FOR TESTING OF AN INTEGRATED CIRCUIT  
Techniques for efficiently performing scan tests are described. In an aspect, a single test pin may be used for both a scan input and a scan output for a scan chain. This multiplexing may reduce...
US20140223251 Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Scan-Test  
A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test...
US20120166903 MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST  
A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test...
US20110145666 ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION  
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan...
US20120096324 TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT  
The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and...
US20120017130 CIRCUIT FOR TESTING INTEGRATED CIRCUITS  
An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test...
US20100031103 Selecting a Scan Topology  
A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection event and a selection sequence...
US20140082446 Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test  
A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test...
US20140075256 Multiple-Capture DFT System for Detecting or Locating Crossing Clock-Domain Faults During Self-Test or Scan-Test  
A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test...
US20100031104 Automatic Scan Format Selection Based on Scan Topology Selection  
A method for specifying a signaling protocol to be used by a controller in a group of controllers connected with shared signaling is provided in which the controller is selected based on selection...
US20090217115 Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy  
A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited...
US20080082880 METHOD OF TESTING HIGH-SPEED IC WITH LOW-SPEED IC TESTER  
A low-frequency circuit tester tests a high-frequency circuit to determine whether the circuit will operate properly at its specified operating frequency when clocked by a clock signal having a...
US20080282122 SINGLE SCAN CLOCK IN A MULTI-CLOCK DOMAIN  
Herein described are at least a method and a system to perform scan testing of an integrated circuit chip. The integrated circuit chip is scan tested using only a single scan clock. The single...
US20100083064 SCANNABLE D FLIP-FLOP  
The present invention relates to scannable D flip-flops, which are improved to solve the problem of the conventional designs and provides a small and fast scannable D flip-flop without...
US20150058690 SCAN TEST CIRCUIT WITH SCAN CLOCK  
A scan test circuit includes: a pulse generator, for generating differential pulses according to a system clock signal; a functional path, including: a D-type latch clocked by the differential...
US20090132881 DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS  
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for...
US20080270860 Integrated Circuit for Writing and Reading Registers Distributed Across a Semiconductor Chip  
An integrated circuit on a semiconductor chip with a plurality of registers distributed across the semiconductor chip. The registers are writeable and readable. The integrated circuit comprises a...
US20070124635 INTEGRATION CIRCUIT AND TEST METHOD OF THE SAME  
An object of the present invention is to realize an at-speed test on a latch-to-latch path (a cross domain path) between different clock domains. In order to achieve the object, the present...
US20110296266 Self-Adjusting Critical Path Timing of Multi-Core VLSI Chip  
A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit....
US20110066906 Pulse Triggered Latches with Scan Functionality  
Described embodiments provide a scan chain including at least one pulse-triggered latch scan cell. The pulse-triggered latch scan cell includes a pulse-triggered latch adapted to latch data...
US20100169728 Decoupled clocking in testing architecture and method of testing  
A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism....
US20070300112 SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS, TEST CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND TEST METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS  
A semiconductor integrated circuit apparatus includes: a plurality of flip-flops configured to operate with clocks having mutually different frequencies; an oscillator configured to output...
US20100257417 COMPRESSING TEST RESPONSES USING A COMPACTOR  
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can...
US20120179945 REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY  
Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it...
US20100313090 Scanning-capable latch device, scan chain device, and scanning method with latch circuits  
In a scanning-capable latch circuit, main latch circuits respectively corresponding to data inputs D1 to D4 are connected in series and, except the last-stage main latch circuit, the scanning...
US20150185283 HANDLING SLOWER SCAN OUTPUTS AT OPTIMAL FREQUENCY  
An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer....
US20100011264 MULTI-CLOCK SYSTEM-ON-CHIP WITH UNIVERSAL CLOCK CONTROL MODULES FOR TRANSITION FAULT TEST AT SPEED MULTI-CORE  
A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for...

Matches 1 - 50 out of 183 1 2 3 4 >