Applications in Class 714/729

Matches 1 - 50 out of 171

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Match	Document	Document Title
1	US20140101505	CLOCK CONTROL FOR REDUCING TIMING EXCEPTIONS IN SCAN TESTING OF AN INTEGRATED CIRCUIT An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality...
2	US20090217117	Low power scan shifting with random-like test patterns An apparatus and method to design an integrated circuit (IC) to reduce the toggling during shifting in and shifting out of test patterns in a IC having scan chains, while maintaining random-like...
3	US20130055041	Scan Test Circuitry Comprising Scan Cells with Multiple Scan Inputs An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises scan cells configured to form...
4	US20140157071	LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement...
5	US20130097468	LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement...
6	US20110289371	LOW POWER SCAN AND DELAY TEST METHOD AND APPARATUS Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement...
7	US20110231721	LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the...
8	US20120297262	ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known...
9	US20110283154	ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known...
10	US20110161758	ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known...
11	US20120151288	Creating Scan Chain Definition from High-Level Model Using High-Level Model Simulation Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the...
12	US20080235544	Built-in self-test of integrated circuits using selectable weighting of test patterns A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a...
13	US20110099442	ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can...
14	US20110231722	ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection...
15	US20150006987	COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i)...
16	US20110307750	COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i)...
17	US20050044461	Semiconductor device test circuit and semiconductor device A semiconductor device test circuit that prevents unnecessary data from being inputted to a functional macro circuit at the time of testing the functional macro circuit. In a plurality of...
18	US20090089637	Semiconductor test system and test method thereof Disclosed is a semiconductor test system comprised of a semiconductor integrated circuit including a plurality of scan cells arranged in first and second directions, and a scan control circuit...
19	US20120304031	HYBRID TEST COMPRESSION ARCHITECTURE USING MULTIPLE CODECS FOR LOW PIN COUNT AND HIGH COMPRESSION DEVICES This invention uses multiple codecs to efficiently achieve the right balance between compression and coverage for a given design. This application illustrates a simple example using two codecs...
20	US20130246874	POSITION INDEPENDENT TESTING OF CIRCUITS Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
21	US20120317453	POSITION INDEPENDENT TESTING OF CIRCUITS Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
22	US20110209020	POSITION INDEPENDENT TESTING OF CIRCUITS Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
23	US20090019329	Serial scan chain control within an integrated circuit An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38,...
24	US20120210184	Compound Hold-Time Fault Diagnosis Aspects of the invention relate to techniques for diagnosing compound hold-time faults. A profiling-based scan chain diagnosis may be performed on a faulty scan chain to determine observed scan...
25	US20140101500	CIRCUITS AND METHODS FOR FUNCTIONAL TESTING OF INTEGRATED CIRCUIT CHIPS Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The...
26	US20080215943	Generating test sets for diagnosing scan chain failures Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example,...
27	US20130047048	AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan...
28	US20110197102	AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan...
29	US20110078524	AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan...
30	US20130346819	SCAN TESTING OF INTEGRATED CIRCUITS AND ON-CHIP MODULES A method for scan testing an integrated circuit that includes a plurality of on-chip logic modules includes configuring the integrated circuit for module level scan testing and chip level scan...
31	US20110302650	INITIATION OF STORAGE DEVICE SCANS Example embodiments relate to initiation of storage device scans based on a record of existing scans of the storage device. In particular, example embodiments include a mechanism that maintains a...
32	US20120324303	INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH PARALLEL REORDERED SCAN CHAINS An integrated circuit comprises scan test circuitry and additional internal circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan...
33	US20140149816	Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit...
34	US20120331361	METHOD AND APPARATUS FOR BROADCASTING SCAN PATTERNS IN A SCAN-BASED INTEGRATED CIRCUIT A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit...
35	US20140245090	PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus...
36	US20130318414	SYSTEM, METHOD AND COMPUTER-ACCESSIBLE MEDIUM FOR DESIGN FOR TESTABILITY SUPPORT FOR LAUNCH AND CAPTURE OF POWER REDUCTION IN LAUNCH-OFF-CAPTURE TESTING Exemplary system, method and computer accessible medium that can transform a circuit by selecting at least one scan cell as an interface register and inserting a shadow register into each...
37	US20080288841	SYSTEM AND METHODS OF BALANCING SCAN CHAINS AND INSERTING THE BALANCED-LENGTH SCAN CHAINS INTO HIERARCHICALLY DESIGNED INTEGRATED CIRCUITS. A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes...
38	US20090083595	Scan test circuit When a dynamic fault test is to be performed on a plurality of divisional circuits, in order to perform the dynamic fault test also on a circuit in which the divisional circuits are combined, and...
39	US20080320351	LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement...
40	US20090265596	SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF An integrated circuit package comprising a semiconductor device and pins is provided. The semiconductor device comprises first and second scan chains, each having an input port and an output port....
41	US20090113265	LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS ON ATE A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects,...
42	US20090132879	MULTIPLEXING OF SCAN INPUTS AND SCAN OUTPUTS ON TEST PINS FOR TESTING OF AN INTEGRATED CIRCUIT Techniques for efficiently performing scan tests are described. In an aspect, a single test pin may be used for both a scan input and a scan output for a scan chain. This multiplexing may reduce...
43	US20140095952	ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan...
44	US20120233512	Two-Dimensional Scan Architecture Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for...
45	US20110055649	TESTING SECURITY OF MAPPING FUNCTIONS Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one...
46	US20080244345	FAILURE DIAGNOSTIC APPARATUS, FAILURE DIAGNOSTIC SYSTEM, AND FAILURE DIAGNOSTIC METHOD There is provided a failure diagnostic apparatus that diagnoses a semiconductor integrated circuit device for failure based on a compressed signal obtained by compressing a plurality of signals...
47	US20120246531	SYSTEM AND METHOD FOR DEBUGGING SCAN CHAINS Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and...
48	US20090106613	TESTING A CIRCUIT WITH COMPRESSED SCAN CHAIN SUBSETS A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan...
49	US20080040637	DIAGNOSING MIXED SCAN CHAIN AND SYSTEM LOGIC DEFECTS Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system...
50	US20090217115	Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited...

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