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US20140115413 FAULT DICTIONARY BASED SCAN CHAIN FAILURE DIAGNOSIS  
A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in...
US20120239993 Method and Apparatus for Fault Injection  
The present invention provides various circuits for injecting faults into a larger circuit, sometimes called circuit under test, or CUT. One type of fault injection circuit is a clock controlled...
US20140115412 SCAN CHAIN FAULT DIAGNOSIS  
Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one...
US20130219237 SCAN CHAIN FAULT DIAGNOSIS  
Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one...
US20140164859 Dynamic Design Partitioning For Scan Chain Diagnosis  
Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit...
US20130268817 Fully X-Tolerant, Very High Scan Compression Scan Test Systems And Techniques  
Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density...
US20140372821 Scan Chain Stitching For Test-Per-Clock  
Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are...
US20150204945 HYBRID ON-CHIP CLOCK CONTROLLER TECHNIQUES FOR FACILITATING AT-SPEED SCAN TESTING AND SCAN ARCHITECTURE SUPPORT  
Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for...
US20140189453 HIGH DENSITY LOW POWER SCAN FLIP-FLOP  
A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate...
US20140013176 ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION  
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known...
US20130246871 ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION  
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known...
US20140331097 MANAGING REDUNDANCY REPAIR USING BOUNDARY SCANS  
An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may...
US20140237310 Test Architecture for Characterizing Interconnects in Stacked Designs  
Aspects of the invention relate to ring-oscillator-based test architecture for characterizing interconnects in stacked designs. The disclosed ring-oscillator-based test architecture comprises a...
US20130166976 Diagnosis-Aware Scan Chain Stitching  
Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design...
US20130185608 SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS  
Stacked integrated circuits (ICs) having a base component and secondary component are tested. The base component has a scan input pad, a scan output pad, a base scan chain, and a base chain access...
US20140143621 SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN INTEGRATED CIRCUIT  
An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The...
US20150089314 POSITION INDEPENDENT TESTING OF CIRCUITS  
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
US20140304563 POSITION INDEPENDENT TESTING OF CIRCUITS  
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
US20140040691 POSITION INDEPENDENT TESTING OF CIRCUITS  
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
US20090307547 Integrated circuit board with JTAG functions  
In an integrated circuit board, a plurality of integrated circuits to be checked are connected together in a star shape. Operation clock data for JTAG of each integrated circuit and check data for...
US20140101500 CIRCUITS AND METHODS FOR FUNCTIONAL TESTING OF INTEGRATED CIRCUIT CHIPS  
Circuits and methods are provided for debugging an integrated circuit. An integrated circuit includes core circuitry, scan test circuitry, scan control circuitry, and debug control circuitry. The...
US20130346816 METHOD AND APPARATUS FOR TESTING I/O BOUNDARY SCAN CHAIN FOR SOC'S HAVING I/O'S POWERED OFF BY DEFAULT  
Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include...
US20140250342 AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL  
Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan...
US20150212153 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20150058688 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20140237311 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20130179743 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20080307279 SERIAL SCAN CHAIN IN A STAR CONFIGURATION  
A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase...
US20090106612 ENHANCING SPEED OF SIMULATION OF AN IC DESIGN WHILE TESTING SCAN CIRCUITRY  
A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a...
US20060179374 Wireless hardware debugging  
Embodiments disclosed relate to wireless debugging of digital circuitry. A boundary scan system for debugging a digital circuit includes a boundary scan interface configured to couple to the...
US20140149815 SYSTEM AND METHOD FOR PROGRAMMING CHIPS ON CIRCUIT BOARD THROUGH BOUNDARY SCAN TECHNOLOGY  
A system and a method for programming chips on circuit board through boundary scan technology are provided. Each chip and a Joint Test Action Group (JTAG) interface on a target circuit board are...
US20140258798 TEST CONTROL POINT INSERTION AND X-BOUNDING FOR LOGIC BUILT-IN SELF-TEST (LBIST) USING OBSERVATION CIRCUITRY  
Test control point insertion and x-bounding for Logic Built-In Self-Test (LBIST) using observation circuitry. In some embodiments, LBIST circuitry may include a plurality of test control circuits...
US20140040688 LOW POWER SCAN FLIP-FLOP CELL  
A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first...
US20150226796 GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES  
Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example,...
US20150143190 PARTIAL SCAN CELL  
An integrated circuit 2 is provided with a serial scan chain. Disposed between at least some serial scan cells 32, 34 forming a serial scan chain there is provided a partial scan cells 36. These...
US20140344636 Method and Apparatus for Broadcasting Scan Patterns in a Scan-Based Integrated Circuit  
A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit...
US20090083594 Testing Functional Boundary Logic at Asynchronous Clock Boundaries of an Integrated Circuit Device  
Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths...
US20120198295 POSITION INDEPENDENT TEST OF CIRCUITS  
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and...
US20140223249 SYSTEM AND METHOD FOR SCAN CHAIN RE-ORDERING  
A system for re-ordering a scan chain of an electronic circuit design using an electronic design automation (EDA) tool includes a processor and a memory in communication with the processor. The...
US20140208175 AT-SPEED SCAN TESTING OF CLOCK DIVIDER LOGIC IN A CLOCK MODULE OF AN INTEGRATED CIRCUIT  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality...
US20150160294 PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES  
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access...
US20140013175 PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES  
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access...
US20120117435 PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES  
The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access...
US20130262944 SCAN CHAIN MODIFICATION FOR REDUCED LEAKAGE  
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is...
US20150253386 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY  
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection...
US20150095730 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY  
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection...
US20140122953 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY  
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection...
US20130227365 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY  
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection...
US20130103995 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY  
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection...
US20080263420 TEST STANDARD INTERFACES AND ARCHITECTURES  
In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is...