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US20130117619 LOGIC CORRUPTION VERIFICATION  
A computer-implemented method of verifying logic in a simulation-based behavioral latch model by performing actions including: inserting a value checking module in the behavioral latch model, the...
US20120166900 TESTING CIRCUITS  
A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is...
US20130061103 Scan Chain Fault Diagnosis  
Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one...
US20140136912 COMBO DYNAMIC FLOP WITH SCAN  
A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static...
US20130111286 SCAN ENABLE TIMING CONTROL FOR TESTING OF SCAN CELLS  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having...
US20150026531 POWER SUPPLY MONITOR FOR DETECTING FAULTS DURING SCAN TESTING  
Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage...
US20110047425 On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis  
On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while...
US20110022908 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS  
A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level...
US20150143189 COVERAGE ENHANCEMENT AND POWER AWARE CLOCK SYSTEM FOR STRUCTURAL DELAY-FAULT TEST  
Methods and devices applying to a clock system of scan circuits to enhance the test coverage for structural delay-fault tests are provided. According to an aspect, a method applying to a clock...
US20120173940 ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS  
A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system is modeled selectively at a register-transfer level (RTL) or a...
US20140223248 ASICS HAVING PROGRAMMABLE BYPASS OF DESIGN FAULTS  
A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This...
US20140189453 HIGH DENSITY LOW POWER SCAN FLIP-FLOP  
A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate...
US20050273683 Insertion of embedded test in RTL to GDSII flow  
A method of designing a scan testable integrated circuit with embedded test objects for use in scan testing the circuit, comprises compiling a register-transfer level (RTL) circuit description of...
US20130297980 Method of Diagnosable Scan Chain  
Embodiments of the present invention relate to a method and apparatus for diagnosing a scan chain. Specifically, a method for a scan chain according to one embodiment of the present invention...
US20140229779 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST  
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence...
US20120210181 SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST  
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence...
US20130007547 EFFICIENT WRAPPER CELL DESIGN FOR SCAN TESTING OF INTEGRATED CIRCUITS  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains,...
US20120204072 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS  
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement...
US20130031433 METHOD FOR PARTITIONING SCAN CHAIN  
A system and method for scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device is provided. One or more scan partitions in the embedded logic circuit are...
US20090235134 TEST PATTERN GENERATION FOR DIAGNOSING SCAN CHAIN FAILURES  
Embodiments of the disclosed technology comprise techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution. For example, certain...
US20120030532 STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING  
A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of...
US20130305107 ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES  
Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection...
US20100318864 Fault location estimation device, fault location estimation method, and program  
A fault location estimation device includes: a faulty scan chain identification unit that identifies a faulty scan chain and its fault type based on result of operation verification test; a faulty...
US20120284577 ARCHITECTURE, SYSTEM, METHOD, AND COMPUTER-ACCESSIBLE MEDIUM FOR ELIMINATING SCAN PERFORMANCE PENALTY  
Exemplary apparatus, methods, and computer-accessible medium can be provided for transforming a circuit. For example, it is possible to select, from the circuit, at least one scan cell which...
US20120278671 CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES  
A method includes shifting a first logic sequence into a first scan chain having a first plurality of scan blocks coupled together, outputting a second logic sequence from each of the plurality of...
US20100031092 METHOD FOR OPERATING A SECURE SEMICONDUCTOR IP SERVER TO SUPPORT FAILURE ANALYSIS  
A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic...
US20130219236 Controlling Scan Access to a Scan Chain  
A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device...
US20130246869 ENHANCED DIAGNOSIS WITH LIMITED FAILURE CYCLES  
Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example,...
US20110126064 ENHANCED DIAGNOSIS WITH LIMITED FAILURE CYCLES  
Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example,...
US20110314514 METHOD AND APPARATUS FOR PROVIDING SCAN CHAIN SECURITY  
A scan chain security capability is provided herein. The scan chain security capability enables secure control over normal use of a scan chain of a system, e.g., for purposes such as testing prior...
US20150067423 A Q-GATING CELL ARCHITECTURE TO SATIATE THE LAUNCH-OFF-SHIFT (LOS) TESTING AND AN ALGORITHM TO IDENTIFY BEST Q-GATING CANDIDATES  
A method for creating an architecture to support Q-gating for launch-off-shift (LOS) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal...
US20100083199 Increasing Scan Compression By Using X-Chains  
To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on...
US20090013226 BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY  
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection...
US20070168804 BURN-IN TEST CIRCUIT, BURN-IN TEST METHOD, BURN-IN TEST APPARATUS, AND A BURN-IN PATTERN GENERATION PROGRAM PRODUCT  
A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of...
US20140047292 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS  
A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems...
US20100306606 COMPACTOR INDEPENDENT DIRECT DIAGNOSIS OF TEST HARDWARE  
Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test...
US20060041806 Testing method for semiconductor device and testing circuit for semiconductor device  
There is provided a testing method for a semiconductor device which has a test object circuit, a non-test object circuit, and a plurality of register circuits which carry out fetching and holding...
US20100031100 Series Equivalent Scans Across Multiple Scan Topologies  
Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one...
US20080222470 SCAN TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND SCAN ENABLE SIGNAL TIME CONTROL CIRCUIT  
A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external...
US20050066189 Methods and structure for scan testing of secure systems  
Circuit structures and associated methods of operation for preventing retrieval of secure information within an integrated circuit by unauthorized use of scan test operation of the integrated...
US20150128001 Efficient Apparatus and Method for Testing Digital Shadow Logic Around Non-Logic Design Structures  
A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled...
US20120216088 GENERATING TEST SETS FOR DIAGNOSING SCAN CHAIN FAILURES  
Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example,...
US20060242508 Simultaneous scan testing for identical modules  
A system 100 for scan testing at least two substantially identical modules 140 and 150 within an integrated circuit is provided. The system 100 includes a first module 140 to receive and process...
US20140129885 SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF  
An exemplary scan clock generator for providing a plurality of on-chip scan clocks to a plurality of cells under test includes: a receiving circuit, arranged for receiving an off-chip scan clock;...
US20120246529 LOW-POWER AND AREA-EFFICIENT SCAN CELL FOR INTEGRATED CIRCUIT TESTING  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having...
US20100299566 DEBUGGING MODULE FOR ELECTRONIC DEVICE AND METHOD THEREOF  
A debugging module for connecting an IC to a JTAG debugger device includes a JTAG interface, an earphone circuit, a USB interface, a switching unit, and a reset circuit. The earphone circuit is...
US20130173976 Scan Test Circuitry with Delay Defect Bypass Functionality  
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having...
US20090259898 Test vector generating method and test vector generating program of semiconductor logic circuit device  
The X-type of each bit permutation is determined (step 301). When there are X-types except for X-type 1, i.e., X-type with no don't-care bits, total capture state transition numbers TECTA1 and...
US20070016834 Reducing Power Dissipation During Sequential Scan Tests  
A scan cell which provides two data outputs, one of use in scan mode and another in functional mode. The functional mode output is connected to functional portions, and transitions on the...
US20080072111 Method for performing a test case with a LBIST engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit  
The present invention relates to a method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected...

Matches 1 - 50 out of 375 1 2 3 4 5 6 7 8 >