Matches 1 - 50 out of 69 1 2 >


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US20100306591 METHOD AND SYSTEM FOR PERFORMING TESTING ON A DATABASE SYSTEM  
There is provided a system and method for performing testing on a database system comprising a query optimizer, the query optimizer having an optimizer plan space comprising a plurality of query...
US20110246830 Creating Virtual Appliances  
Techniques for creating a virtual appliance in a virtualization environment are provided. The techniques include implementing a framework, wherein the framework comprises a knowledge...
US20110289354 Distributed Batch Runner  
Method and systems for allocating test scripts across a plurality of test machines is described. A set of test scripts may be maintained where the set of test scripts includes a plurality of test...
US20110093744 Distributed Batch Runner  
Method and systems for allocating test scripts across a plurality of test machines is described. A set of test scripts may be maintained where the set of test scripts includes a plurality of test...
US20130238936 PARTIAL FAULT TOLERANT STREAM PROCESSING APPLICATIONS  
In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing...
US20110239048 PARTIAL FAULT TOLERANT STREAM PROCESSING APPLICATIONS  
In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing...
US20130179735 CONCURRENT TEST INSTRUMENTATION  
A program can be instrumented to test the program. The test instruments are classified, and concurrency constraints applied based on the classifications. A testing tool determines classifications...
US20120089868 FUZZ TESTING OF ASYNCHRONOUS PROGRAM CODE  
A fuzz testing system is described herein that represents event sources, channels, processors, and consumers as first-class entities in an application. Abstracting event-related entities allows...
US20130305091 DRAG AND DROP NETWORK TOPOLOGY EDITOR FOR GENERATING NETWORK TEST CONFIGURATIONS  
There is disclosed a method and apparatus for editing test configurations. The method includes displaying a graphical representation of a test configuration to be tested by a test system on a user...
US20110320872 HIERARCHICAL ERROR INJECTION FOR COMPLEX RAIM/ECC DESIGN  
A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on...
US20100070803 Sequencer and test system including the sequencer  
A test system 100 that can accept a plurality of plug-in electronic cards in Xi Slots 126 or PXI slots 134 is described. The test or source measure switching system 100 includes a sequencer or...
US20140250329 SYSTEM LEVEL ARCHITECTURE VERIFICATION FOR TRANSACTION EXECUTION IN A MULTI-PROCESSING ENVIRONMENT  
Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device...
US20070011492 Generation of trace data  
An apparatus and method for processing data is disclosed. The apparatus comprises a data processing circuit operable over a sequence of processing cycles to perform data processing operations in...
US20090235121 AUTOMATED SPECIFICATION BASED FUNCTIONAL TEST GENERATION INFRASTRUCTURE  
A method comprising the steps of (A) generating a code, (B) applying one or more constraint constructs to the code, (C) generating a coverage code and a second code in response to applying the...
US20100042874 DEVICE TESTING METHOD AND ARCHITECTURE  
The same testing equipment can be used to test devices operating under different protocols. Where the testing protocol is slower than the native serial protocol of the high-speed serial link...
US20090055687 RAM diagnosis device and RAM diagnosis method  
A RAM diagnosis device sequentially generates a state bit indicating any one of states of kinds of processing; selects processing referring to the state bit. The devices then writes a first data...
US20130305090 TEST CONFIGURATION RESOURCE MANAGER  
A test configuration resource manager and a method of managing test configuration resources in a network test system. A computer readable storage medium may store instructions that, when executed,...
US20110099426 SYSTEM FOR INJECTING PROTOCOL SPECIFIC ERRORS DURING THE CERTIFICATION OF COMPONENTS IN A STORAGE AREA NETWORK  
An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing...
US20100017658 TEST SYSTEM AND METHOD WITH A SIMULATOR  
A test system for testing various functions of electronic devices includes a master device and a simulation control device. The master device is connected to an input device and the electronic...
US20110138229 Automated Testing of Software with Targeting of Deep Paths  
A method is provided for generating a test case for testing a program, which can include analyzing instructions of the program to identify basic blocks and superblocks, each basic block containing...
US20090271661 STATUS TRANSITION TEST SUPPORT DEVICE, STATUS TRANSITION TEST SUPPORT METHOD, AND RECORDING MEDIUM  
A status transition table generation portion generates a status transition table containing combination information cells provided in the form of a matrix for describing information corresponding...
US20110283142 METHOD AND SYSTEM FOR PERFORMING PARALLEL COMPUTER TASKS  
A method and system for performing parallel tasks in a computer system includes invoking a single-threaded operating environment in a computer, invoking under the single-threaded operating...
US20120131386 VERIFICATION OF SPECULATIVE EXECUTION  
A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT...
US20090259890 Method & apparatus for hardware fault management  
A hardware health evaluation module is associated with a hardware module or device and employs a linked list of error records to continually evaluate the state of the hardware module to determine...
US20090300420 Method for Testing at Least One Arithmetic Unit Installed in a Control Unit  
A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a...
US20100287412 SOFTWARE RELIABILITY TEST METHOD USING SELECTIVE FAULT ACTIVATION, TEST AREA RESTRICTION METHOD, WORKLOAD GENERATION METHOD AND COMPUTING APPARATUS FOR TESTING SOFTWARE RELIABILITY USING THE SAME  
Provided are a software reliability test method using selective fault activation, a test area restriction method, a workload generation method and a computing apparatus for testing software...
US20050223292 Single instruction type based hardware patch controller  
A patch mechanism is described, which can be used to detect and workaround defects and conditions existing in an integrated circuit chip. The patch mechanism includes a trigger-matching logic...
US20100332905 PROGRAM EXECUTION DEVICE AND METHOD FOR CONTROLLING THE SAME  
Conventionally, when executing a plurality of programs while being synchronized by a plurality of debuggers, an interface has been required for performing a particular coordination between the...
US20120137178 STREAM BASED DEBUGGING TECHNIQUES  
Techniques are described for debugging a processing element (or elements) in a stream based database application in a manner that reduces the impact of debugging the processing element (or...
US20130067281 TESTING SYSTEM AND METHOD FOR HANDHELD ELECTRONIC DEVICE  
A handheld electronic device testing system and a method for testing a handheld electronic device installed with an open operating platform and installed with a test instruction execution program...
US20110173499 System of Testing Engineered Safety Feature Instruments  
The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is...
US20140136898 Run-Time Default Detection in a Component Associated with an Application Programming Interface Platform  
Methods and apparatuses for fault detection in a component associated with an application programming interface platform are provided. In an embodiment, the component is determined to have been...
US20120210171 COGNITIVE AGENT  
Aspects relate to a cognitive agent that performs functions associated with a desired result. The functions performed by cognitive agent supplement other activities performed at a same time. In...
US20100058111 ABNORMALITY DETECTION METHOD FOR ELECTRONIC DEVICE CONNECTED BY LOOP, AND ELECTRONIC DEVICE  
An electronic device is connected to a loop transmission line via a bypass circuit and detects being bypassed from the loop transmission line. Each electronic device connected to a looped...
US20110197090 Error Reporting Through Observation Correlation  
A software component is executed to carry out a task, the task including a subtask. An external function is called to perform the subtask, the external function executing in a separate thread or...
US20110258490 Testing Components for Thread Safety  
A checking system is described for determining whether a component is thread safe in the course of interacting with two or threads in a client environment. The checking system uses a manual,...
US20140143600 DEBUGGING IN A SEMICONDUCTOR DEVICE TEST ENVIRONMENT  
A test system that enables real-time interactive debugging of a device under test (DUT) using native customer code. A translation module may format, in real time, debug commands, corresponding to...
US20110072309 Debugger for Multicore System  
A debugger includes: a plurality of processor cores; and a scheduler configured to control an allocation of a plurality of basic modules to the processor cores based on an execution rule for...
US20100100766 TEST APPARATUS  
A test apparatus for testing a portable communication unit. The test apparatus comprises a test unit adapted to supply test input data to the portable communication unit and retrieve test output...
US20100293413 PROCESS-WINDOW AWARE DETECTION AND CORRECTION OF LITHOGRAPHIC PRINTING ISSUES AT MASK LEVEL  
In one aspect of the invention, a method provides a calibrated critical-failure model for a printing process of a critical feature by virtue of a classification of an optical parameter space...
US20100218045 DISTRIBUTED RUNTIME DIAGNOSTICS IN HIERARCHICAL PARALLEL ENVIRONMENTS  
A technique is disclosed for distributed runtime diagnostics in hierarchical parallel environments. In one embodiment, a user is allowed to configure, during runtime, a processing element on which...
US20120311387 METHOD AND APPARATUS FOR LOAD TESTING ONLINE SERVER SYSTEMS  
A method includes capturing data that is representative of actions performed by each of a plurality of human user operated clients as they interact with an online software application, loading at...
US20100037100 METHOD AND SYSTEM FOR ISOLATING SOFTWARE COMPONENTS  
A software testing system operative to test a software application comprising a plurality of software components, at least some of which are highly coupled hence unable to support a dependency...
US20110154113 DATA STORAGE DEVICE TESTER  
A data storage device (DSD) tester for testing a DSD is disclosed. The DSD tester comprises control circuitry operable to receive a DSD log from the DSD, wherein the DSD log comprises at least one...
US20080320331 CONTROL APPARATUS  
For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator (2) has processor...
US20080155330 METHODS AND APPARATUS FOR DEBUGGING A WORKFLOW PROCESS  
The present disclosure provides methods and apparatuses for debugging a workflow. Using the methods and apparatus herein, users can utilize common debugging constructs such as watch variables,...
US20100095156 INFORMATION PROCESSING APPARATUS AND CONTROL METHOD  
A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output...
US20100299561 SYSTEMS AND METHODS FOR MANAGING TESTING FUNCTIONALITIES  
Described herein are systems and methods for managing testing functionalities. One such method includes receiving, from a test tool, data indicative of a user-created test script, being a...
US20130254595 COMMUNICATION SYSTEM AND TEST APPARATUS  
An instruction is assuredly transmitted. A test apparatus that tests a device under test, includes a test unit that tests a device under test by exchanging a signal with the device under test, a...
US20050240820 Method and apparatus for multiprocessor debug support  
A device having at least one processor connected a controller and a memory; where the controller to execute a debug process. The debug process attaches a breakpoint bit field to each instruction....

Matches 1 - 50 out of 69 1 2 >