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US20060059387 Processor condition sensing circuits, systems and methods  
A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.
US20070214389 JTAG power collapse debug  
A method of performing a debug operation on a processor after a power collapse is provided. An idle state of the processor is detected during an execution mode of the processor. The idle state is...
US20070106965 Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same  
Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting...
US20160188433 TESTING AND MITIGATION FRAMEWORK FOR NETWORKED DEVICES  
The present disclosure generally relates to the automated testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases...
US20080016396 TEST EMULATOR, TEST MODULE EMULATOR AND RECORD MEDIUM STORING PROGRAM THEREIN  
There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test...
US20060277435 Mechanism for storing and extracting trace information using internal memory in microcontrollers  
It is the object of the present invention to provide a mechanism to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor...
US20050102573 In-circuit configuration architecture for embedded configurable logic array  
A system-on-a-chip integrated circuit that includes a configurable logic array, a processor core, and a memory adapted to store instructions for a mission function, and instructions for a...
US20080168310 Hardware diagnostics and software recovery on headless server appliances  
Described is a headless server appliance configured with a secondary actuation mechanism that when actuated, enters the headless server appliance into a diagnostic mode. For example, the...
US20100251023 SYSTEM AND METHOD FOR IMPROVED PERFORMANCE AND OPTIMIZATION OF DATA EXCHANGES OVER A COMMUNICATIONS LINK  
A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a...
US20100023807 TEST DEVICE AND METHOD FOR THE SOC TEST ARCHITECTURE  
A test device for the SoC test architecture is disclosed. The device comprises plural test groups connected in parallel and a test control flag register within a controller. Each test group...
US20070220337 Microcomputer  
A microcomputer includes: a memory; a CPU which decodes memory data stored in the memory to execute an instruction; a debug control section for instructing the microcomputer to perform a debug...
US20080005617 AUTOMATED PROCESSING OF ELECTRONIC LOG BOOK PILOT REPORTS FOR GROUND-BASED FAULT PROCESSING  
Automated processing of electronic log book (ELB) pilot reports (PIREPs) are configured to receive ELB PIREPs and prioritize observed faults and potential observed faults included in the ELB...
US20050257087 Test circuit topology reconfiguration and utilization method  
Among the embodiments of the present invention is a technique that includes executing a first protocol on test bus (40) in accordance with an established test standard to operate a first topology...
US20050066232 Debug circuit  
The present invention provide a debug circuit which has a structure in which a conversion block latches plural internal signals which are supposed to be effective in finding a cause of a...
US20130238933 MULTI-CORE SOC HAVING DEBUGGING FUNCTION  
There present invention relates to a multi-core System On Chip (SoC) having a debugging function. The multi-core SoC having a debugging function includes one or more processors each configured to...
US20050262396 APPARATUS AND METHOD FOR AUTOMATED TEST SETUP  
Apparatus and methods for setting up a test instrument to perform measurements on a circuit having a plurality of signal applied to a plurality of output pins. Configuration parameters including...
US20140258780 MEMORY CONTROLLERS INCLUDING TEST MODE ENGINES AND METHODS FOR REPAIR OF MEMORY OVER BUSSES USED DURING NORMAL OPERATION OF THE MEMORY  
Examples of memory controllers are described that may repair a memory using a bus between the memory controller and the memory. The memory controllers may include a test mode engine able to place...
US20160124826 SEMICONDUCTOR DEVICE AND METHOD FOR TESTING RELIABILITY OF SEMICONDUCTOR DEVICE  
A semiconductor memory includes a memory controller including a plurality of processing circuits. The plurality of processing units includes an encryption/decryption unit that encrypts and...
US20080229149 REMOTE TESTING OF COMPUTER DEVICES  
In embodiments of the present invention improved capabilities are described for a method and system of software testing that may used on a computer network, the network may include a plurality of...
US20080282110 SCAN CLOCK ARCHITECTURE SUPPORTING SLOW SPEED SCAN, AT SPEED SCAN, AND LOGIC BIST  
Herein described are at least a method and a system to perform scan testing of an integrated circuit chip using one or more internal and external clock sources. In a representative embodiment, the...
US20060150019 Semiconductor device, test apparatus and measurement method therefor  
A semiconductor device for measuring delay time of a wiring under test provided therein is provided, wherein the semiconductor device includes: a loop path on which the wiring under test is...
US20080313499 DEBUG CIRCUIT  
The present invention provide a debug circuit which has a structure in which a conversion block latches plural internal signals which are supposed to be effective in finding a cause of a...
US20050283669 Edge detect circuit for performance counter  
An edge detect circuit connected to a bus carrying data is described. In one embodiment, the edge detect circuit comprises logic for detecting an edge of a raw increment signal and logic for...
US20070288797 Generating scan test vectors for proprietary cores using pseudo pins  
A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At...
US20110276829 CLIENT SERVER AND METHOD FOR MONITORING FUNCTION TESTS THEREOF  
A client server and a test monitoring method for the client server include receiving a customization Intelligent Platform Management Interface (IPMI) from the monitor server and parsing the...
US20080263400 Fault insertion system  
A method of scheduling a simulated hardware fault on a computer system by specifying at least a termination point where the simulated hardware fault will be automatically removed from the computer...
US20060179348 Method and apparatus for representing, managing and problem reporting in RFID networks  
A method, system and computer product for determining the source of problems in a Radio Frequency Identification (RFID) network containing a plurality of component are disclosed. The method...
US20110113286 SCAN TEST CIRCUIT AND SCAN TEST METHOD  
A scan test circuit for a memory with a first memory cell column, a second memory cell column that replaces a failed column of the first memory cell column, a first switching circuit that connects...
US20100011250 MICROCONTROLLER INFORMATION EXTRACTION SYSTEM AND METHOD  
A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a...
US20140149795 INFORMATION PROCESSING APPARATUS AND METHOD RELATING TO HARDWARE DIAGNOSIS  
A disclosed apparatus includes a memory and circuitry that is configured to execute an operating system, and realize one or plural logical domains that provide a predetermined function as a...
US20140013156 METHOD AND SYSTEM FOR MANAGING IMAGE FORMING APPARATUS THROUGH NETWORK  
A method of managing an image forming apparatus through a network, the method including: logging in to a server through a diagnostic control unit application from a user terminal; receiving, by...
US20090287959 SYSTEM AND METHOD FOR TESTING COMPUTER  
A test system includes at least one computer and a control circuit for testing the computer. The computer includes an input interface and an output interface. The control circuit is configured for...
US20070088983 Integrated circuit comprising a measurement unit for measuring utlization  
The invention provides an integrated circuit comprising a data processing system which performs satisfactorily after integration of the individual building blocks, such as main processors and...
US20100180154 Built In Self-Test of Memory Stressor  
A method and system for generating addresses in a memory card built in self-test (MCBIST) for testing memory devices. The method includes receiving a MCBIST command and determining an addressing...
US20100042870 MULTICORE PROCESSOR AND METHOD OF CONTROLLING MULTICORE PROCESSOR  
A multicore processor has a plurality of processor cores each of which is configured to execute a computation, a plurality of reconfigurable devices dynamically reconfigurable in circuit...
US20070266349 DIRECTED RANDOM VERIFICATION  
A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested...
US20060248391 State machine-based command line debugger  
An apparatus for debugging an IC chip including an interface for converting serial off-chip data to parallel on-chip data and for converting parallel on-chip data to serial off-chip data and a...
US20060206763 Debugging system, semiconductor integrated circuit device, microcomputer, and electronic apparatus  
A debugging system, comprising a pin-saving type debug tool and a target system to be a debug target of the debug tool, the target system includes: an integrated circuit device incorporating a CPU...
US20050102574 Apparatus and method for performing boundary scans using fixed and variable signal groups  
In a JTAG test and debug environment, the signal groups may have a variable length, a fixed length or a combination of both fixed and variable signal groups to be transferred to the target...
US20130151902 DEBUG SYSTEM AND METHOD  
A debug system includes a debug device and a computer. The debug device includes an IIC reading and writing module, a first control module; and a signal receiving and transmitting module. The...
US20140173346 VALIDATING OPERATION OF SYSTEM-ON-CHIP CONTROLLER FOR STORAGE DEVICE USING PROGRAMMABLE STATE MACHINE  
A system-on-chip includes a storage controller, a read channel integrated circuit, a programmable state machine controller, a switching circuit, a buffer memory, and an interface to access the...
US20070168729 System and method for testing and debugging electronic apparatus in single connection port  
A method applied in a test host for testing and debugging an electronic apparatus is provided. The test host and the electronic apparatus are connected by a connection port. The method comprises...
US20100064143 SYSTEM LSI  
A system LSI comprising: a processor which processes confidential data; a first on-chip bus which is connected to the processor; a working memory which saves the confidential data processed by the...
US20060195722 Pattern generator and testing apparatus  
There is provided a pattern generator that generates a test pattern for performing a scan test for an electronic device. The pattern generator includes: a main memory that stores a scan pattern...
US20050088277 System consisting of a household appliance and an external apparatus  
A system for connecting a household appliance to an external apparatus for the purpose of parameterizing, error diagnosing and remotely maintaining the former by an exchange of electromagnetic...
US20070174700 Connector ports for anti-tamper  
An anti-tamper system including an interface key having a first surface and a second surface, the interface key adapted to mate with a test connector at the first surface and adapted to mate with...
US20130151903 IMAGE FORMING APPARATUS  
An image forming apparatus has a plurality of device modules for executing predetermined functions; and a control module for controlling operation of the device modules. The control module...
US20060224922 Integrated circuit and method for sending requests  
In networks on an integrated circuit a first module typically has access to an address space, wherein addresses identify locations within second modules. It may be necessary to address two or more...
US20130198566 Method and Apparatus for Debugging System-on-Chip Devices  
A device that provides debug mode information associated with a System-on-Chip (SoC) device includes a multiplexer, debug controller, and a memory device internal to the SoC device and coupled to...
US20080222452 TEST APPARATUS FOR TESTING A CIRCUIT UNIT  
Test apparatus for testing a circuit unit. A first test device is arranged outside the circuit unit. A second test device, which is arranged integrally with the circuit unit, has a sample-and-hold...
Matches 1 - 50 out of 71 1 2 >