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US20070266349 DIRECTED RANDOM VERIFICATION  
A directed random verification system and method analyzes a pair of generated test cases, from a pool of generated test cases which are capable of testing at least a portion of an untested...
US20120089870 BIOS REFRESH DEVICE AND METHOD USING THE SAME  
A BIOS refresh device includes a first socket, a second socket, and a jumper. The first socket includes a first elastic contact, a first voltage contact, and a first ground contact. The second...
US20130031411 COMPUTER SYSTEM AND DIAGNOSTIC METHOD THEREOF  
A computer system and a diagnostic method thereof are provided. The computer system comprises a system management bus (SMBus) switch, a plurality of servers and a remote management controller...
US20060101309 Debugging simulation of a circuit core using pattern recorder, player & checker  
Debugging a simulation of a circuit core uses a pattern recorder, a pattern player and a pattern checker to record input stimuli provided to a first core, record output generated by the first core...
US20080148100 CONTROL PANEL ASSEMBLY METHOD FOR A FITNESS EQUIPMENT METER  
The present invention is a control panel assembly method for a fitness equipment meter. The processors of the A/D module and IC module are integrated into a single processor, namely, all control...
US20050283669 Edge detect circuit for performance counter  
An edge detect circuit connected to a bus carrying data is described. In one embodiment, the edge detect circuit comprises logic for detecting an edge of a raw increment signal and logic for...
US20100070803 Sequencer and test system including the sequencer  
A test system 100 that can accept a plurality of plug-in electronic cards in Xi Slots 126 or PXI slots 134 is described. The test or source measure switching system 100 includes a sequencer or...
US20130055024 CENTRAL PROCESSING UNIT TEST SYSTEM  
A central processing unit (CPU) test system includes a CPU socket, a CPU core controller, and a CPU test device. The CPU core controller stores a start voltage message. The CPU test device...
US20140157051 METHOD AND DEVICE FOR DEBUGGING A MIPS-STRUCTURE CPU WITH SOUTHBRIDGE AND NORTHBRIDGE CHIPSETS  
The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches,...
US20140215269 TEST INFRASTRUCTURE SIMULATION  
Systems, methods, and machine-readable and executable instructions are provided for operating a test infrastructure simulation. Operating a test infrastructure simulation can include executing a...
US20070288797 Generating scan test vectors for proprietary cores using pseudo pins  
A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At...
US20110041010 SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE  
A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a...
US20150089288 TECHNIQUE FOR ESTABLISHING AN AUDIO SOCKET DEBUG CONNECTION  
A debug controller monitors a tip-ring-ring-shield (TRRS) socket, within a form factor device, to detect whether a debug unit is transmitting a request for a TRRS socket debug connection. The form...
US20150261637 Self-Diagnosis Device and Self-Diagnosis Method  
A detailed execution schedule of self-diagnosis processing is set according to various requests. A self-diagnosis device includes a plurality of functional blocks, a storage unit that stores a...
US20110276829 CLIENT SERVER AND METHOD FOR MONITORING FUNCTION TESTS THEREOF  
A client server and a test monitoring method for the client server include receiving a customization Intelligent Platform Management Interface (IPMI) from the monitor server and parsing the...
US20130159771 Accelerated Processing Unit Debugging Using a Graphics Processing Unit Centric Debug Core  
An Accelerated Processing Unit (APU) comprising a central processing unit (CPU) core portion and a graphics processing unit (GPU) core portion coupled to the CPU core portion. The GPU core portion...
US20090300419 REALTIME TEST RESULT PROMULGATION FROM NETWORK COMPONENT TEST DEVICE  
The technology disclosed relates to real-time collection and flexible reporting of test data. In particular, it is useful when collecting packet counts during tests of network devices that...
US20060015776 Built-in computer power-on memory test method  
A built-in computer power-on memory test method, wherein a memory test program is built into the BIOS unit of the motherboard, immediately displays a menu on the screen at computer power-on, with...
US20100115337 VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD)  
A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of...
US20080168310 Hardware diagnostics and software recovery on headless server appliances  
Described is a headless server appliance configured with a secondary actuation mechanism that when actuated, enters the headless server appliance into a diagnostic mode. For example, the...
US20070220335 Hardware function isolating during slow mode initial program loading  
A computer implemented method, apparatus, and computer usable program code for performing a diagnostic in a hardware component established in a data processing system. The method includes starting...
US20080282110 SCAN CLOCK ARCHITECTURE SUPPORTING SLOW SPEED SCAN, AT SPEED SCAN, AND LOGIC BIST  
Herein described are at least a method and a system to perform scan testing of an integrated circuit chip using one or more internal and external clock sources. In a representative embodiment, the...
US20080229149 REMOTE TESTING OF COMPUTER DEVICES  
In embodiments of the present invention improved capabilities are described for a method and system of software testing that may used on a computer network, the network may include a plurality of...
US20060179348 Method and apparatus for representing, managing and problem reporting in RFID networks  
A method, system and computer product for determining the source of problems in a Radio Frequency Identification (RFID) network containing a plurality of component are disclosed. The method...
US20070088985 Protection of a digital quantity contained in an integrated circuit comprising a JTAG interface  
A method and a circuit for protecting a digital quantity stored in a microcontroller including a JTAG interface, including the step of making the digital quantity dependent from a value stored in...
US20100318848 Establishing a connection between a testing and/or debugging interface and a connector  
This invention relates to automatically establishing a connection between a testing and/or debugging interface to an integrated circuit and a connector of an apparatus, the connector being...
US20090055685 Electronic apparatus in which functioning of of a microcomputer is monitored by another microcomputer to detect abnormal operation  
In an electronic apparatus, a first microcomputer is monitored by a second microcomputer, which periodically transmits data relating to a main function to the first microcomputer to be processed....
US20080010527 Method of solving BIST failure of CPU by means of BIOS and maximizing system performance  
The present invention is to provide a method of solving BIST (Build-in Self Test) failure of CPU (Central Process Unit) by means of BIOS (Basic Input/Output System) and maximizing system...
US20060015775 System and method for observing the behavior of an integrated circuit (IC)  
A system and method for observing the functional behavior of a target circuit. In one embodiment, a first interface, which is external with respect to the target circuit, is provided for...
US20120137176 MICROCOMPUTER  
A debug circuit of a microcomputer, providing an on-chip debug function, is provided as a measurement permission circuit for outputting a measurement permission signal to a timer that measures, as...
US20100023807 TEST DEVICE AND METHOD FOR THE SOC TEST ARCHITECTURE  
A test device for the SoC test architecture is disclosed. The device comprises plural test groups connected in parallel and a test control flag register within a controller. Each test group...
US20080034255 PROGRAM FAILURE ANALYSIS SYSTEM, FAILURE ANALYSIS METHOD, AND EMULATOR DEVICE  
A CPU forced stop signal is used as means for stopping execution of a program executed on a ROM by a CPU of a target system. A time required for stopping the CPU from the issuance of the CPU...
US20050223290 Enhanced diagnostic fault detection and isolation  
A system and method for enhanced diagnostic fault detection and isolation is provided, wherein COTS/MOTS subsystems of a system under test are evaluated in a hierarchical manner providing improved...
US20050268169 Method and system for editing logical programmes for trouble diagnostics  
The invention concerns a method and a system for editing logical programs for a trouble diagnostic system, which trouble diagnostic system is used to determine and locate trouble in industrial...
US20120151263 DEBUG STATE MACHINES AND METHODS OF THEIR OPERATION  
Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to...
US20130042144 EDRAM MACRO DISABLEMENT IN CACHE MEMORY  
A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being...
US20100070802 SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREFOR  
A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection...
US20100011249 DEVICE FOR TESTING A FUNCTION OF A DISPLAY PORT, AND SYSTEM AND METHOD FOR TESTING THE SAME  
A device is disclosed for testing the function of a display port. The device includes a display port transmitting part, a field programmable gate array, and a memory. The display port transmitting...
US20070174700 Connector ports for anti-tamper  
An anti-tamper system including an interface key having a first surface and a second surface, the interface key adapted to mate with a test connector at the first surface and adapted to mate with...
US20130055023 VERIFICATION OF SOC SCAN DUMP AND MEMORY DUMP OPERATIONS  
Techniques are disclosed for verifying memory dump operations and scan dump operations. A memory specification is analyzed and parsed to generate a script for performing a memory dump operation....
US20120060058 TESTING OF NON STUCK-AT FAULTS IN MEMORY  
A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell,...
US20150089289 PROGRAMMABLE INTERFACE-BASED VALIDATION AND DEBUG  
A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A...
US20070006032 Associating program execution sequences with performance counter events  
Software performance may be improved by collecting and correlating performance counter events and program execution state information. On each successive callback of performance counter data, a...
US20100064173 MECHANISM FOR STORING AND EXTRACTING TRACE INFORMATION USING INTERNAL MEMORY IN MICRO CONTROLLERS  
This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory...
US20100031089 Dynamic Broadcast of Configuration Loads Supporting Multiple Transfer Formats  
A method for dynamically broadcasting configuration information to controllers connected in a scan topology in a target system is provided in which a selection event followed by the configuration...
US20140281717 BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL  
A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first...
US20050114733 Concurrent I/O  
A DUT has a multiple scan paths, at least one per I/O pin. That is, instead of one scan path for every two pins there is one scan path for every pin, thus effectively doubling the number of scan...
US20130124920 METHOD, APPARATUS and product FOR testing transactions  
A computer-implemented method and apparatus, comprising: having a plurality of processing entities operating substantially concurrently in a computerized platform enabling transaction operations,...
US20060195722 Pattern generator and testing apparatus  
There is provided a pattern generator that generates a test pattern for performing a scan test for an electronic device. The pattern generator includes: a main memory that stores a scan pattern...
US20050088277 System consisting of a household appliance and an external apparatus  
A system for connecting a household appliance to an external apparatus for the purpose of parameterizing, error diagnosing and remotely maintaining the former by an exchange of electromagnetic...

Matches 1 - 50 out of 190 1 2 3 4 >