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US20120284490 WORKING SET PROFILER  
A working set profiler can monitor an execution of a program or can monitor a user-specified portion of a program to identify methods executed within the monitored execution and associate memory...
US20130246772 RUN-TIME INSTRUMENTATION INDIRECT SAMPLING BY INSTRUCTION OPERATION CODE  
Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by instruction operation code. An aspect of the invention includes a method for implementing run-time...
US20120084538 Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor  
A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all...
US20090287907 System for providing trace data in a data processor having a pipelined architecture  
The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline,...
US20090217012 MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS  
An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and...
US20110154121 CONCURRENCY TEST EFFICTIVENESS VIA MUTATION TESTING AND DYNAMIC LOCK ELISION  
One embodiment described herein is directed to a method practiced in a computing environment. The method includes acts for determining test suite effectiveness for testing for concurrency problems...
US20150039868 INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING  
Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at...
US20090217010 DATA PROCESSOR DEVICE HAVING TRACE CAPABILITIES AND METHOD  
In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to...
US20050223364 Method and apparatus to compact trace in a trace buffer  
A method and apparatus to compact trace in a trace buffer are described.
US20090249045 APPARATUS AND METHOD FOR CONDENSING TRACE INFORMATION IN A MULTI-PROCESSOR SYSTEM  
A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a...
US20130311757 EXTRACT CPU TIME FACILITY  
An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating...
US20090265530 Latency hiding of traces using block coloring  
An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information....
US20110119651 TECHNIQUES RELATED TO CUSTOMIZATIONS FOR COMPOSITE APPLICATIONS  
A framework is provided for enabling and managing customizations to an application. In one embodiment, techniques are provided that enable the customizability of an application to be controlled...
US20110138359 MODIFIED IMPLEMENTATION OF JAVA DEBUG WIRE PROTOCOL  
A client debugger application or a virtual machine includes a receiving module configured to receive a command packet of a debugging protocol from a computer. The command packet includes an...
US20120254628 CIPHER MESSAGE EXECUTION IN A COMPUTING SYSTEM  
A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or...
US20110225400 Device for Testing a Multitasking Computation Architecture and Corresponding Test Method  
A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation...
US20130339685 RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION  
Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained....
US20110320783 VERIFICATION USING OPCODE COMPARE  
A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding...
US20140281436 METHOD FOR EMULATING A GUEST CENTRALIZED FLAG ARCHITECTURE BY USING A NATIVE DISTRIBUTED FLAG ARCHITECTURE  
A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front...
US20070283133 Reducing bandwidth required for trace data  
A data processing apparatus is disclosed comprising: trace logic for monitoring behaviour of a portion of said data processing apparatus; and prediction logic operable to provide at least one...
US20130326202 LOAD TEST CAPACITY PLANNING  
Disclosed herein are techniques for load test capacity planning. Resources consumed by instructions executing in a first computer apparatus are determined. A metric associated with a second...
US20130246768 TRANSFORMING NON-CONTIGUOUS INSTRUCTION SPECIFIERS TO CONTIGUOUS INSTRUCTION SPECIFIERS  
Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the...
US20120198216 ENHANCED MONITOR FACILITY  
A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is...
US20110078421 ENHANCED MONITOR FACILITY  
A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is...
US20150019846 SYSTEM LEVEL ARCHITECTURE VERIFICATION FOR TRANSACTION EXECUTION IN A MULTI-PROCESSING ENVIRONMENT  
Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device...
US20110219217 System on Chip Breakpoint Methodology  
A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured...
US20140195785 FORMAL VERIFICATION OF A LOGIC DESIGN  
A method is provided for verification of a logic design for a processor execution unit which includes an instruction pipeline with one or more pipeline stages. The method includes: creating a...
US20130091342 TRACING SOFTWARE EXECUTION OF A BUSINESS PROCESS  
Various embodiments of systems and methods to trace an execution of a business process are disclosed. Business rules and corresponding business objects required to execute the business process are...
US20060294343 Realtime compression of microprocessor execution history  
A trace compression unit is included in a processor system that has a processor core and an external system memory. The trace compression unit encrypts the processor core execution history into...
US20150058604 VERIFYING FORWARDING PATHS IN PIPELINES  
A tool for formally verifying forwarding paths in an information pipeline. The tool creates two logic design copies of the pipeline to be verified. The tool retrieves a first and a second...
US20090276610 TEST CASE GENERATION WITH BACKWARD PROPAGATION OF PREDEFINED RESULTS AND OPERAND DEPENDENCIES  
A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards...
US20120179898 SYSTEM AND METHOD FOR ENFORCING SOFTWARE SECURITY THROUGH CPU STATISTICS GATHERED USING HARDWARE FEATURES  
This disclosure is directed to measuring hardware-based statistics, such as the number of instructions executed in a specific section of a program during execution, for enforcing software...
US20090300427 METHOD OF LOGGING STACK TRACE INFORMATION  
A computer system comprises a memory configured to store software instructions; a set of registers; and a processing unit configured to temporarily store passed parameters in the set of registers...
US20130205124 BRANCH TARGET COMPUTATION  
Embodiments related to conducting and constructing a secure start-up process are disclosed, One embodiment provides, on a computing device, a method of conducting a secure start-up process. The...
US20080082802 Microcomputer debugging system  
A microcomputer debugging system capable of executing a plurality of debug modes, wherein processing is not allowed to shift to an interruption program during a debugging operation in one of the...
US20090313460 TRACE COMPRESSION METHOD FOR DEBUG AND TRACE INTERFACE OF MICROPROCESSOR  
The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers...
US20060031662 Processor implementing conditional execution and including a serial queue  
A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile...
US20080184014 METHOD FOR EFFICIENTLY EMULATING COMPUTER ARCHITECTURE CONDITION CODE SETTINGS  
Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of...
US20090187747 SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS  
A system and method for tracing instruction pointers and data access is disclosed. In one embodiment the system includes a plurality of trace units including at least one first trace unit...
US20080046699 Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking  
Methods and apparatus are provided for non-deterministic incremental program replay using checkpoints and syndrome tracking. Replay of a program proceeds by, for a given execution of the program,...
US20060259750 SELECTIVELY EMBEDDING EVENT-GENERATING INSTRUCTIONS  
An information carrier medium containing debugging software that, when executed by a processor, causes the processor to receive information from hardware in communication with the processor, the...
US20050188186 Obtaining execution path information in an instruction sampling system  
A method of linking control transfer information with sampling information for instructions executing in a processor which includes storing information relating to execution events, selecting an...
US20100251160 MEASUREMENT AND REPORTING OF PERFORMANCE EVENT RATES  
Methods and systems are disclosed for measuring performance event rates at a computer and reporting the performance event rates using timelines. A particular method tracks, for a time period, the...
US20080263338 EXCEPTION OPERATION APPARATUS, METHOD AND COMPUTER PROGRAM FOR CONTROLLING DEBUGGING APPARATUS, AND TELEVISION AND CELLULAR PHONE PROVIDING THE SAME  
In order to automatically activate a debugger while maintaining the status of the machine as it was just before execution of the instruction which has raised an exception even in a case in which a...
US20070050607 Alteration of execution of a program in response to an execution-optimization information  
Embodiments include a device, and a method. In an embodiment, a device includes an information store operable to save an execution-optimization information, a first processor, and a hardware...
US20110131396 TIMING ANALYSIS  
One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to...
US20090307468 Generating a Test Case Micro Generator During Processor Design Verification and Validation  
A main generator generates a micro generator and initial test cases based upon a processor architecture specifications and user input, such as general purpose register availability, translation...
US20070288728 CPU utilization metering on sytems that include multiple hardware threads per core  
Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core, combining the active thread...
US20100017583 Call Stack Sampling for a Multi-Processor System  
A computer implemented method, apparatus, and computer usable program code for sampling call stack information. Responsive to identifying an interrupt, a determination is made as to whether all...
US20110219216 Mechanism for Performing Instruction Scheduling based on Register Pressure Sensitivity  
A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure...

Matches 1 - 50 out of 295 1 2 3 4 5 6 >