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US20080098207 Analyzing diagnostic data generated by multiple threads within an instruction stream  
A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple...
US20050038978 Reconfigurable processing system and method  
A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field...
US20070050608 Hardware-generated and historically-based execution optimization  
Embodiments include a device, and a method. In an embodiment, a device includes a processor operable to execute an instruction set, a communications link exposed to an execution-optimization...
US20070050606 Runtime-based optimization profile  
Embodiments include a device, and a method. In an embodiment, a device includes a microengine operatively coupled with a processor having an instruction set. The microengine includes a microengine...
US20110258421 Architecture Support for Debugging Multithreaded Code  
Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system,...
US20080086627 METHODS AND APPARATUS TO ANALYZE COMPUTER SOFTWARE  
Methods and apparatus to analyze computer software are disclosed. The disclosed methods and apparatus may be used to verify and validate computer software. An example method includes receiving...
US20050114639 Hardened extensible firmware framework to support system management mode operations using 64-bit extended memory mode processors  
A hardened extensible firmware framework to support system management mode (SMM) operations using 64-bit extended memory mode processors. A firmware-based framework enables drivers to register and...
US20050033945 Dynamically changing the semantic of an instruction  
A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic...
US20080133897 Diagnostic apparatus and method  
A diagnostic method is described for generating diagnostic data relating to processing of an instruction stream, wherein said instruction stream has been compiled from a source instruction stream...
US20060031662 Processor implementing conditional execution and including a serial queue  
A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile...
US20150234661 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM USING THE SAME  
A processor system, includes a first central processing unit (CPU) that executes a redundant instruction set; and a second CPU that executes the redundant instruction set, wherein before the...
US20120084537 SYSTEM AND METHOD FOR EXECUTION BASED FILTERING OF INSTRUCTIONS OF A PROCESSOR TO MANAGE DYNAMIC CODE OPTIMIZATION  
A filter executing on a processor monitors instructions executing on the processor to identify instructions that will benefit from performance tuning. Filtering instructions before analysis for...
US20100017583 Call Stack Sampling for a Multi-Processor System  
A computer implemented method, apparatus, and computer usable program code for sampling call stack information. Responsive to identifying an interrupt, a determination is made as to whether all...
US20080046699 Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking  
Methods and apparatus are provided for non-deterministic incremental program replay using checkpoints and syndrome tracking. Replay of a program proceeds by, for a given execution of the program,...
US20050091474 Fuse configurable alternate behavior of a central processing unit  
A method, system and apparatus are provided for alternating instruction sets in central processing units. A microcontroller is provided with a configuration mechanism, such as a fuse that,...
US20050091480 Computer system and method for executing interrupt instructions in operating modes  
A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier...
US20090187747 SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS  
A system and method for tracing instruction pointers and data access is disclosed. In one embodiment the system includes a plurality of trace units including at least one first trace unit...
US20050223364 Method and apparatus to compact trace in a trace buffer  
A method and apparatus to compact trace in a trace buffer are described.
US20140281434 PATH PROFILING USING HARDWARE AND SOFTWARE COMBINATION  
A mechanism for generating a path profile is disclosed. A profiling module may insert profiling instructions into instruction blocks. The profiling instructions may generate a path identifier as a...
US20080235700 Hardware Monitor Managing Apparatus and Method of Executing Hardware Monitor Function  
A hypervisor OS includes a monitor context table in which plural monitor contexts each including monitor operation conditions and information concerning priority are set in order to set a hardware...
US20080189528 System, Method and Software Application for the Generation of Verification Programs  
A system, method and software application according to the present invention creates complex, interesting, self checking and sturdy verification programs. A self-checking random verification...
US20060277395 Processor performance monitoring  
Systems, methods, and device are provided for monitoring a processor. One method embodiment includes selectively combining micro-architectural events into various groups of micro-architectural...
US20050071611 Method and apparatus for counting data accesses and instruction executions that exceed a threshold  
A method, apparatus, and computer instructions in a data processing system for processing instructions. An instruction is received at a processor in the data processing system. If an indicator is...
US20050071608 Method and apparatus for selectively counting instructions and data accesses  
A method, apparatus, and computer instructions in a data processing system for processing instructions. Instructions are received at a processor in the data processing system. If an indicator is...
US20090249046 APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION  
A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor...
US20070118725 CPU life-extension apparatus and method  
A CPU life-extension apparatus and method makes a processor appear to be an upgraded CPU to substantially all software applications accessed thereby, thereby reducing the need and expense of...
US20080313442 DEBUGGING TECHNIQUES FOR A PROGRAMMABLE INTEGRATED CIRCUIT  
Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer...
US20080082802 Microcomputer debugging system  
A microcomputer debugging system capable of executing a plurality of debug modes, wherein processing is not allowed to shift to an interruption program during a debugging operation in one of the...
US20080077780 System and Method for Software Debugging  
The software debugging system provides a processor that is executing a software process, and the software process has a bug or other failure. A fast-response reporter circuit connects to a low...
US20100122072 Debugging system, debugging method, debugging control method, and debugging control program  
A debugging system according to an exemplary embodiment of the present invention includes: a plurality of arithmetic processing units (51, 52) that perform arithmetic processing; a comparison unit...
US20080082801 APPARATUS AND METHOD FOR TRACING INSTRUCTIONS WITH SIMPLIFIED INSTRUCTION STATE DESCRIPTORS  
A method of tracing processor instructions includes characterizing processor state changes in accordance with simplified instruction state descriptors. The simplified instruction state descriptors...
US20120179898 SYSTEM AND METHOD FOR ENFORCING SOFTWARE SECURITY THROUGH CPU STATISTICS GATHERED USING HARDWARE FEATURES  
This disclosure is directed to measuring hardware-based statistics, such as the number of instructions executed in a specific section of a program during execution, for enforcing software...
US20160077836 PREDICTING LITERAL LOAD VALUES USING A LITERAL LOAD PREDICTION TABLE, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA  
Predicting literal load values using a literal load prediction table, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit...
US20060294343 Realtime compression of microprocessor execution history  
A trace compression unit is included in a processor system that has a processor core and an external system memory. The trace compression unit encrypts the processor core execution history into...
US20140156975 Redundant Threading for Improved Reliability  
In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second...
US20130024674 RETURN ADDRESS OPTIMISATION FOR A DYNAMIC CODE TRANSLATOR  
A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware...
US20060064570 Method and apparatus for automatically generating test data for code testing purposes  
One embodiment of the present invention provides a system that automatically generates test data for code testing purposes. During operation, the system receives code under test (CUT). The system...
US20050071612 Method and apparatus for generating interrupts upon execution of marked instructions and upon access to marked memory locations  
A method, apparatus, and computer instructions in a data processing system for processing instructions. An instruction is identified for execution within a processor in the data processing system....
US20110289302 DATA PROCESSING DEVICE AND METHOD  
Overhead is significant when a timestamp according to a reference time is inserted. In view of this, there is provided an LSI which includes: a first time information conversion unit which...
US20050071610 Method and apparatus for debug support for individual instructions and memory locations  
A method, apparatus, and computer instructions in a data processing system for monitoring processing of instructions and memory locations. An instruction is received in the data processing system...
US20130326202 LOAD TEST CAPACITY PLANNING  
Disclosed herein are techniques for load test capacity planning. Resources consumed by instructions executing in a first computer apparatus are determined. A metric associated with a second...
US20060117122 Method and apparatus for conditionally obfuscating bus communications  
Illustrative embodiments of the present invention include, but are not limited to, a system (including associated apparatus and methods practiced thereon) for conditionally obfuscating internal...
US20090307468 Generating a Test Case Micro Generator During Processor Design Verification and Validation  
A main generator generates a micro generator and initial test cases based upon a processor architecture specifications and user input, such as general purpose register availability, translation...
US20080177990 Synthesized assertions in a self-correcting processor and applications thereof  
The present invention provides one or more synthesized assertions in a self-correcting processor, and applications thereof. In an embodiment, a synthesized assertion detects a mismatch between...
US20090187748 METHOD AND SYSTEM FOR DETECTING STACK ALTERATION  
The disclosed systems and methods relate to employing one or more of machine instructions (i.e. assembler language instructions) to detect stack alterations. Aspects of the present invention also...
US20050071609 Method and apparatus to autonomically take an exception on specified instructions  
A method, apparatus, and computer instructions in a data processing system for monitoring the execution of a program. Instructions for calls and returns in the program are associated with a set of...
US20120221838 SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES  
The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that...
US20110225400 Device for Testing a Multitasking Computation Architecture and Corresponding Test Method  
A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation...
US20090222646 METHOD AND APPARATUS FOR DETECTING PROCESSOR BEHAVIOR USING INSTRUCTION TRACE DATA  
A method and apparatus for detecting processor behavior in real time using instruction trace data, in one aspect, identifies one or more call addresses from which a function to be observed is...
US20080270770 Method for Optimising the Logging and Replay of Mulit-Task Applications in a Mono-Processor or Multi-Processor Computer System  
This invention relates to a system and method for the management, more particularly by external, transparent and non-intrusive control, of the running of one or more software tasks within a...

Matches 1 - 50 out of 87 1 2 >