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US20130262842 CODE GENERATION METHOD AND INFORMATION PROCESSING APPARATUS  
An information processing apparatus generates first and second trees representing a dependency relationship among instructions from first code. The information processing apparatus then adjusts...
US20140032882 MODIFICATION OF FUNCTIONALITY IN EXECUTABLE CODE  
In an example embodiment, an instruction set is accessed. An instruction modifier is associated with the instruction set. Thereafter, the instruction set is transformed into a modified instruction...
US20120246452 Signature Update by Code Transformation  
Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a...
US20100299504 MICROPROCESSOR WITH MICROINSTRUCTION-SPECIFIABLE NON-ARCHITECTURAL CONDITION CODE FLAG REGISTER  
A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set...
US20140149723 DYNAMIC EVALUATION AND ADAPTION OF HARDWARE HASH FUNCTIONS  
Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective...
US20150143087 SERVICE SYSTEM AND METHOD  
A system includes provision of a first set of instructions associated with a product to a user of the product, the user having one or more associated characteristics, reception of a revision to...
US20100115247 REPLACEMENT POLICY FOR HOT CODE DETECTION  
Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage...
US20140108772 Exploiting an Architected Last-Use Operand Indication in a System Operand Resource Pool  
A pool of available physical registers are provided for architected registers, wherein operations are performed that activate and deactivate selected architected registers, such that the...
US20130086369 COMPILING CODE FOR AN ENHANCED APPLICATION BINARY INTERFACE (ABI) WITH DECODE TIME INSTRUCTION OPTIMIZATION  
Compiling code for an enhanced application binary interface (ABI) including identifying, by a computer, a code sequence configured to perform a variable address reference table function including...
US20140089638 Multi-Destination Instruction Handling  
Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality...
US20120198209 GUEST INSTRUCTION BLOCK WITH NEAR BRANCHING AND FAR BRANCHING SEQUENCE CONSTRUCTION TO NATIVE INSTRUCTION BLOCK  
A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one...
US20120204016 Rewriting Branch Instructions Using Branch Stubs  
Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a...
US20100138703 IDENTIFYING AND MONITORING ASYNCHRONOUS TRANSACTIONS  
Monitoring asynchronous transactions in a computing environment is disclosed. A first unique identifier is determined when a first method executes. The identifier is associated with an...
US20110125986 Reducing inter-task latency in a multiprocessor system  
A method of reducing inter-task latency for software comprising a sequence of instructions including a synchronous remote procedure call to be executed on a multiprocessor system comprising a...
US20130246766 TRANSFORMING NON-CONTIGUOUS INSTRUCTION SPECIFIERS TO CONTIGUOUS INSTRUCTION SPECIFIERS  
Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the...
US20130332710 MODULATING DYNAMIC OPTIMAIZATIONS OF A COMPUTER PROGRAM  
Technologies and implementations for modulating dynamic optimizations of a computer program during execution are generally disclosed.
US20150261540 CONDITIONAL INSTRUCTION END OPERATION  
A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made...
US20150261539 CONDITIONAL INSTRUCTION END OPERATION  
A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made...
US20140281431 EFFICIENT WAY TO CANCEL SPECULATIVE 'SOURCE READY' IN SCHEDULER FOR DIRECT AND NESTED DEPENDENT INSTRUCTIONS  
A method and apparatus for simultaneously canceling a dependent instruction and a nested dependent instruction when a cancel timer of a source of the dependent instruction and a cancel timer of a...
US20130311755 RUNNING STATE POWER SAVING VIA REDUCED INSTRUCTIONS PER CLOCK OPERATION  
A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to...
US20090089560 INFRASTRUCTURE FOR PARALLEL PROGRAMMING OF CLUSTERS OF MACHINES  
GridBatch provides an infrastructure framework that hides the complexities and burdens of developing logic and programming application that implement detail parallelized computations from...
US20150205610 CONFIGURING MANAGED SYSTEMS USING ABSTRACTED FUNCTIONS  
Systems and methods for configuring managed systems using abstracted functions. An example method may include: receiving a command corresponding to one or more instructions in a defined protocol,...
US20120124343 APPARATUS AND METHOD FOR MODIFYING INSTRUCTION OPERAND  
Provided are an apparatus and method for modifying an instruction operand. The apparatus includes a first selector configured to receive first instruction operands and a second selector configured...
US20120216022 CONTROLLING THE SELECTIVELY SETTING OF OPERATIONAL PARAMETERS FOR AN ADAPTER  
An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters,...
US20130339682 METHODS TO OPTIMIZE A PROGRAM LOOP VIA VECTOR INSTRUCTIONS USING A SHUFFLE TABLE AND A MASK STORE TABLE  
According to one embodiment, a code optimizer is configured to receive first code having a program loop implemented with scalar instructions to store values of a first array to a second array...
US20140304493 METHODS AND SYSTEMS FOR PERFORMING A BINARY TRANSLATION  
Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions....
US20080091926 OPTIMIZATION OF A TARGET PROGRAM  
A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information...
US20130117536 RECONFIGURABLE INSTRUCTION ENCODING METHOD AND PROCESSOR ARCHITECTURE  
A reconfigurable instruction encoding method includes the followings. An instruction distribution of an application is counted, and multiple instruction pairs with higher utilization rates are...
US20110066829 Selecting Regions Of Hot Code In A Dynamic Binary Rewriter  
An approach to region selection which extends beyond traces and selects super-regions. A super-region (SR) contains arbitrary control flow, such as interprocedural nested loops, that provides a...
US20130311756 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION WITHOUT READING CARRY FLAG  
A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand...
US20130173893 HARDWARE COMPILATION AND/OR TRANSLATION WITH FAULT DETECTION AND ROLL BACK FUNCTIONALITY  
Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes...
US20130198495 Method and Apparatus For Register Spill Minimization  
The aspects enable a computing device to allocate memory space to variables during runtime compilation of a software application. A compiler may be modified to identify operations that can be...
US20130268742 CORE SWITCHING ACCELERATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM  
An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on...
US20150106600 EXECUTION OF CONDITION-BASED INSTRUCTIONS  
Execution of condition-based instructions is facilitated. A condition-based instruction is obtained, as well as a confidence level associated with the instruction. The confidence level is checked,...
US20140281430 EXECUTION OF CONDITION-BASED INSTRUCTIONS  
Execution of condition-based instructions is facilitated. A condition-based instruction is obtained, as well as a confidence level associated with the instruction. The confidence level is checked,...
US20110202749 INSTRUCTION COMPRESSING APPARATUS AND METHOD  
An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus...
US20130086368 Using Register Last Use Infomation to Perform Decode-Time Computer Instruction Optimization  
Two computer machine instructions are fetched for execution, but replaced by a single optimized instruction to be executed, wherein a temporary register used by the two instructions is identified...
US20130262839 INSTRUCTION MERGING OPTIMIZATION  
A computer system for optimizing instructions is configured to identify two or more machine instructions as being eligible for optimization, to merge the two or more machine instructions into a...
US20060026401 Method and system to disable the "wide" prefix  
A method and related system to disable the “WIDE” prefix. At least some of the illustrative embodiments may be a method comprising disabling an ability of an opcode to act as a prefix for other...
US20140164746 Tracking Multiple Conditions in a General Purpose Register and Instruction Therefor  
An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in...
US20140164745 REGISTER ALLOCATION FOR CLUSTERED MULTI-LEVEL REGISTER FILES  
A method for allocating registers within a processing unit. A compiler assigns a plurality of instructions to a plurality of processing clusters. Each instruction is configured to access a first...
US20150205611 Stack Pointer Value Prediction  
Methods and apparatus for predicting the value of a stack pointer which store data when an instruction is seen which grows the stack. The information which is stored includes a size parameter...
US20100049954 METHOD FOR SPECULATIVE EXECUTION OF INSTRUCTIONS AND A DEVICE HAVING SPECULATIVE EXECUTION CAPABILITIES  
A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are...
US20150121047 READING A REGISTER PAIR BY WRITING A WIDE REGISTER  
A read operation is initiated to obtain a wide input operand. Based on the initiating, a determination is made as to whether the wide input operand is available in a wide register or in two narrow...
US20150052337 SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING  
Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether...
US20130073838 MULTI-ADDRESSABLE REGISTER FILES AND FORMAT CONVERSIONS ASSOCIATED THEREWITH  
A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be...
US20060101250 Configurable computing machine and related systems and methods  
A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is,...
US20140108771 Using Register Last Use Information to Perform Decode Time Computer Instruction Optimization  
Two computer machine instructions are fetched for execution, but replaced by a single optimized instruction to be executed, wherein a temporary register used by the two instructions is identified...
US20110320785 Binary Rewriting in Software Instruction Cache  
Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target...
US20070050604 Fetch rerouting in response to an execution-based optimization profile  
Embodiments include a device, and a method. In an embodiment, a device includes a processor operable to execute an instruction set, and an execution-optimization circuit. The execution circuit...
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