Matches 1 - 50 out of 283 1 2 3 4 5 6 >


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US20110238956 Collective Acceleration Unit Tree Structure  
A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an...
US20150089204 DYNAMICALLY RECONFIGURABLE MICROPROCESSOR  
A microprocessor includes a plurality of dynamically reconfigurable functional units, a fingerprint, and a fingerprint unit. As the plurality of dynamically reconfigurable functional units execute...
US20110161638 Ising Systems: Helical Band Geometry For DTC and Integration of DTC Into A Universal Quantum Computational Protocol  
Disclosed herein are efficient geometries for dynamical topology changing (DTC), together with protocols to incorporate DTC into quantum computation. Given an Ising system, twisted depletion to...
US20140281419 COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING LOGIC  
An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions,...
US20140129807 APPROACH FOR EFFICIENT ARITHMETIC OPERATIONS  
A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent...
US20120079251 MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS  
A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second...
US20130080740 FAST CONDITION CODE GENERATION FOR ARITHMETIC LOGIC UNIT  
In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution...
US20130227252 Add Instructions to Add Three Source Operands  
A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first,...
US20110153993 Add Instructions to Add Three Source Operands  
A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first,...
US20090235049 METHOD AND APPARATUS FOR QR-FACTORIZING MATRIX ON A MULTIPROCESSOR SYSTEM  
The present invention provides a method and apparatus for QR-factorizing matrix on a multiprocessor system, wherein the multiprocessor system comprises at least one core processor and a plurality...
US20100306504 Controlling issue and execution of instructions having multiple outcomes  
At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second...
US20140325190 METHOD FOR IMPROVING EXECUTION PERFORMANCE OF MULTIPLY-ADD INSTRUCTION DURING COMPILING  
The present invention relates to a method for improving execution performance of multiply-add instructions during compiling, comprising the following steps of: compiling a source code by a...
US20130024668 ARCHITECTURE AND IMPLEMENTATION METHOD OF PROGRAMMABLE ARITHMETIC CONTROLLER FOR CRYPTOGRAPHIC APPLICATIONS  
An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of...
US20130275726 ARITHMETIC PROCESSING APPARATUS AND BRANCH PREDICTION METHOD  
A branch target address table is provided for each branch instruction having a plurality of branch targets. Each branch target address table stores a history of a plurality of branch target...
US20110153994 Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag  
A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second...
US20140237216 MICROPROCESSOR  
A microprocessor according to an aspect of the present invention includes an arithmetic operation unit. The arithmetic operation unit includes: a plurality of arithmetic operation devices arranged...
US20130166890 APPARATUS COMPRISING A PLURALITY OF ARITHMETIC LOGIC UNITS  
An arrangement of at least two arithmetic logic units carries out an operation defined by a decoded instruction including at least one operand and more than one operation code. The operation codes...
US20140006753 MATRIX MULTIPLY ACCUMULATE INSTRUCTION  
A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first...
US20110314263 INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND  
An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second...
US20130212357 Floating Point Constant Generation Instruction  
Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant...
US20110246789 INTEGRATED CIRCUIT PROTECTED AGAINST HORIZONTAL SIDE CHANNEL ANALYSIS  
An integrated circuit including a multiplication function configured to execute a multiplication operation of two binary words x and y including a plurality of basic multiplication steps of...
US20120072703 SPLIT PATH MULTIPLY ACCUMULATE UNIT  
In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second...
US20060101244 Multipurpose functional unit with combined integer and floating-point multiply-add pipeline  
A multipurpose functional unit is configurable to support a number of operations including floating-point and integer multiply-add, operations as well as other integer and/or floating-point...
US20080195848 Vertical and Horizontal Pipelining in a System for Performing Modular Multiplication  
The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical...
US20090198973 PROCESSING CIRCUIT  
A processing circuit according to the present invention includes a plurality of logic circuits (designated as L11, . . . , and L44) formed by arranging in arrays and is configured to input an...
US20120198211 ARITHMETIC UNIT AND ARITHMETIC PROCESSING METHOD FOR OPERATING WITH HIGHER AND LOWER CLOCK FREQUENCIES  
There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from...
US20080288755 CLOCK DRIVEN DYNAMIC DATAPATH CHAINING  
A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also...
US20140189319 Opportunistic Utilization of Redundant ALU  
A processor includes at least one processing core that includes an operation dispatch for dispatching operations from an instruction pipeline, a plurality of arithmetic logic units for executing...
US20130086366 Register File with Embedded Shift and Parallel Write Capability  
An apparatus includes a register file including a logical circuit. The register file is configured to perform one or more logical operations in conjunction with the logical circuit. The logical...
US20110264896 MICROPROCESSOR THAT FUSES MOV/ALU INSTRUCTIONS  
A microprocessor receives first and second program-adjacent macroinstructions of the instruction set architecture of the microprocessor. The first macroinstruction instructs the microprocessor to...
US20090024866 DIGITAL VLSI CIRCUIT AND IMAGE PROCESSING DEVICE INTO WHICH THE SAME IS ASSEMBLED  
A digital VLSI circuit is provided with functions in which the number of switching operations to supply electric power to each arithmetic operation unit is reduced in a restricted period of time...
US20140013086 ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS  
A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without...
US20080162259 ASSOCIATED COMMUNITY PLATFORM  
Embodiments of an associated community platform are shown. Some embodiments comprise a receiver residing on a server to receive data from one or more nodes that are apart of a merchant network, a...
US20130275727 Processors, Methods, Systems, and Instructions to Generate Sequences of Integers in which Integers in Consecutive Positions Differ by a Constant Integer Stride and Where a Smallest Integer is Offset from Zero by an Integer Offset  
A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored...
US20150121043 COMPUTER AND METHODS FOR SOLVING MATH FUNCTIONS  
Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical...
US20090150654 FUSED MULTIPLY-ADD FUNCTIONAL UNIT  
A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The...
US20110035570 MICROPROCESSOR WITH ALU INTEGRATED INTO STORE UNIT  
A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and...
US20090300335 Execution Unit With Inline Pseudorandom Number Generator  
A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be...
US20090049276 Techniques for sourcing immediate values from a VLIW  
Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation...
US20100318771 COMBINED BYTE-PERMUTE AND BIT SHIFT UNIT  
A processor includes a decode unit and a byte permute unit. The byte permute unit receives an instruction from the decode unit. The byte permute unit determines whether the instruction corresponds...
US20080140994 Data-Parallel processing unit  
A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective...
US20140189305 REDUNDANT EXECUTION FOR RELIABILITY IN A SUPER FMA ALU  
A system, processor and method to increase computational reliability by using underutilized portions of a data path with a SuperFMA ALU. The method allows the reuse of underutilized hardware to...
US20080229081 RECONFIGURABLE CIRCUIT, RECONFIGURABLE CIRCUIT SYSTEM, AND RECONFIGURABLE CIRCUIT SETTING METHOD  
Each cell comprises a first selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; a second selector which accepts K-pieces (K is a...
US20070198815 Programmable digital signal processor having a clustered SIMD microarchitecture including a complex short multiplier and an independent vector load unit  
A programmable digital signal processor with a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core, and a complex computing unit. Each of the accelerator...
US20100299505 INSTRUCTION FUSION CALCULATION DEVICE AND METHOD FOR INSTRUCTION FUSION CALCULATION  
An instruction fusion calculation device of the present invention includes an instruction fusion detection circuit, an instruction fusion circuit, and a calculator. The instruction fusion...
US20090300336 Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions  
The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with...
US20120260073 EMULATION OF EXECUTION MODE BANKED REGISTERS  
A microprocessor includes processor modes comprising a user mode and a plurality of exception modes. An execution unit performs arithmetic operations on operands specified by program instructions....
US20060107027 General purpose micro-coded accelerator  
A micro-coded accelerator may comprise multiple programmable control units, multiple special function units, a cross-bar switch to connect any of the control units to any one or more of the...
US20110208952 PROGRAMMABLE CONTROLLER FOR EXECUTING A PLURALITY OF INDEPENDENT SEQUENCE PROGRAMS IN PARALLEL  
A programmable controller which executes a plurality of independent sequence programs in parallel is provided with an ASIC, including a plurality of arithmetic-logic units and a plurality of...
US20100030837 COMBINED ADDER CIRCUIT ARRAY AND/OR PLANE  
A method of modifying a group of full adder circuits to compute a Boolean function of a set number of input bits, each full adder circuit having first and second data inputs, a data output, a...

Matches 1 - 50 out of 283 1 2 3 4 5 6 >