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US20110252222 EVENT COUNTER IN A SYSTEM ADAPTED TO THE JAVACARD LANGUAGE  
The implementation of a counter in a microcontroller adapted to the JavaCard language while respecting the atomicity of a modification of the value of this counter, wherein the counter is reset by...
US20130339676 TRANSACTION ABORT INSTRUCTION  
A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a...
US20130262835 CODE GENERATION METHOD AND INFORMATION PROCESSING APPARATUS  
An information processing apparatus generates first and second operation trees representing a dependency relationship among the instructions included in a first code, and computes first and second...
US20120204017 Microprocessor for Executing Byte Compiled Java Code  
A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal...
US20140365749 USING A SINGLE TABLE TO STORE SPECULATIVE RESULTS AND ARCHITECTURAL RESULTS  
Some implementations provide techniques and arrangements that include a physical register file to store a speculative result of executing a operation and to store an architectural result after the...
US20120159126 Programming Language Exposing Idiom Calls  
A programming language may include hint instructions that may notify a programming idiom accelerator that a programming idiom is coming. An idiom begin hint exposes the programming idiom to the...
US20120060018 Collective Operations in a File System Based Execution Model  
A mechanism is provided for group communications using a MULTI-PIPE synthetic file system. A master application creates a multi-pipe synthetic file in the MULTI-PIPE synthetic file system, the...
US20130339675 RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION  
Task specific diagnostic controls are provided to facilitate the debugging of certain types of abort conditions. The diagnostic controls may be set to cause transactions to be selectively aborted,...
US20110173417 Programming Idiom Accelerators  
A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is...
US20130080744 ABSTRACTING COMPUTATIONAL INSTRUCTIONS TO IMPROVE PERFORMANCE  
Methods and systems for executing a code stream of non-native binary code on a computing system are disclosed. One method includes parsing the code stream to detect a plurality of elements...
US20140129807 APPROACH FOR EFFICIENT ARITHMETIC OPERATIONS  
A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent...
US20120047495 EXECUTION ENVIRONMENT SUPPORT FOR REACTIVE PROGRAMMING  
An execution environment is created or extended to include support for coroutines to facilitate reactive programming. Utilizing functionality provided by an execution environment, such as a...
US20100057727 DETECTION OF RECURRING NON-OCCURRENCES OF EVENTS USING PATTERN MATCHING  
Techniques for detecting recurring non-occurrences of an event. In one embodiment, techniques are provided for detecting the non-occurrence of an event within each of a series of time periods...
US20110131425 SYSTEMS AND METHODS FOR POWER MANAGEMENT IN A HIGH PERFORMANCE COMPUTING (HPC) CLUSTER  
Embodiments of the invention broadly contemplate systems, methods, apparatuses and program products providing a power management technique for an HPC cluster with performance improvements for...
US20140320391 METHODS FOR IMPROVEMENTS IN MOBILE ELECTRONIC DEVICES  
A series of methods are presented to improve the operation and user experience of mobile handheld devices such as mobile phones. The methods include methods allowing useful operation on low...
US20130339673 INTRA-INSTRUCTIONAL TRANSACTION ABORT HANDLING  
Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at...
US20140101412 SPECULATIVE PRIVILEGE ELEVATION  
Systems and methods are provided for speculatively elevating a privilege level at which instructions are executed. In embodiment, this is accomplished b identification of a privilege elevation...
US20130086365 Exploiting an Architected List-Use Operand Indication in a Computer System Operand Resource Pool  
A pool of available physical registers are provided for architected registers, wherein operations are performed that activate and deactivate selected architected registers, such that the...
US20110023035 Command Synchronisation  
The order in which commands issued by a process to one or more hardware processing units should be executed is determined based upon whether the commands are issued to just one hardware processing...
US20130067202 CONDITIONAL NON-BRANCH INSTRUCTION PREDICTION  
A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not...
US20060026388 Computer executing instructions having embedded synchronization points  
A computer operable to execute instructions having embedded synchronization points includes a first program counter and a second program counter. The computer also includes a synchronization unit...
US20120297171 METHODS FOR GENERATING CODE FOR AN ARCHITECTURE ENCODING AN EXTENDED REGISTER SPECIFICATION  
There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width...
US20130246756 HARDWARE PROTOCOL STACK  
Disclosed is a hardware protocol stack, where header information of analysis-subjected protocol is stored in a register unit, comparison is made whether information recorded in the header of...
US20140244979 Estimating Time Remaining for an Operation  
Techniques for estimating time remaining for an operation are described. Examples operations include file operations, such as file move operations, file copy operations, and so on. A wide variety...
US20150019844 SYNTHETIC PROCESSING DIVERSITY WITHIN A HOMOGENEOUS PROCESSING ENVIRONMENT  
A method of increasing processing diversity on a computer system includes: loading a plurality of instruction streams, each of the plurality of instruction streams being equivalent; executing, in...
US20130117543 LOW OVERHEAD OPERATION LATENCY AWARE SCHEDULER  
A method and apparatus for processing multi-cycle instructions include picking a multi-cycle instruction and directing the picked multi-cycle instruction to a pipeline. The pipeline includes a...
US20130339674 RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION  
Restricted instructions are prohibited from execution within a transaction. There are classes of instructions that are restricted regardless of type of transaction: constrained or nonconstrained....
US20120226893 Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity  
A hardware controller includes a first hardware interface, a second hardware interface, first hardware logic, and second hardware logic. The first hardware interface is to couple the hardware...
US20120297170 DECENTRALIZED ALLOCATION OF RESOURCES AND INTERCONNNECT STRUCTURES TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES  
A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of...
US20140317387 METHOD FOR PERFORMING DUAL DISPATCH OF BLOCKS AND HALF BLOCKS  
A method for executing dual dispatch of blocks and half blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form...
US20110320722 MANAGEMENT OF MULTIPURPOSE COMMAND QUEUES IN A MULTILEVEL CACHE HIERARCHY  
An apparatus for controlling access to a pipeline includes a plurality of command queues including a first subset of the plurality of command queues being assigned processes the commands of first...
US20100138703 IDENTIFYING AND MONITORING ASYNCHRONOUS TRANSACTIONS  
Monitoring asynchronous transactions in a computing environment is disclosed. A first unique identifier is determined when a first method executes. The identifier is associated with an...
US20120066483 Computing Device with Asynchronous Auxiliary Execution Unit  
A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured...
US20090216984 OPTIMIZATIONS OF A PERFORM FRAME MANAGEMENT FUNCTION ISSUED BY PAGEABLE GUESTS  
Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host...
US20140157288 METHOD AND APPARATUS FOR PROVIDING CONTEXT AWARE LOGGING  
A method, apparatus and computer program product are therefore provided to enable context aware logging. In this regard, the method, apparatus, and computer program product may record events that...
US20110191754 SYSTEM USING A UNIQUE MARKER WITH EACH SOFTWARE CODE-BLOCK  
A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of...
US20140223151 KERNEL EXECUTION FOR HYBRID SYSTEMS  
A method for executing kernels in a hybrid system includes running a program on a host computer and identifying in an instruction stream of the program a first instruction including a function of...
US20130339672 Next Instruction Access Intent Instruction  
Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an...
US20130086363 Computer Instructions for Activating and Deactivating Operands  
An instruction set architecture (ISA) includes instructions for selectively indicating last-use architected operands having values that will not be accessed again, wherein architected operands are...
US20130297915 FLAG NON-MODIFICATION EXTENSION FOR ISA INSTRUCTIONS USING PREFIXES  
In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode,...
US20120239368 Identifying Initial Don't Care Memory Elements for Simulation  
In an embodiment, the design of a digital circuit may be analyzed to identify which uninitialized memory elements, such as flops, have initial don't care values. The analysis may include...
US20140351564 SIMPLIFICATION OF LARGE NETWORKS AND GRAPHS  
Embodiments relate to simplifying large and complex networks and graphs using global connectivity information based on calculated node centralities. An aspect includes calculating node...
US20130080745 FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY  
Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite...
US20130073836 FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY  
Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite...
US20080229079 APPARATUS, SYSTEM, AND METHOD FOR MANAGING COMMANDS OF SOLID-STATE STORAGE USING BANK INTERLEAVE  
An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is...
US20080312961 Managing Deployment of Clinical Guidelines  
Variable and ambiguous factors in clinical guideline execution are further defined by prior expert medical scrutiny and testing. The definitions promote uniformity and ease of use, afford...
US20130332704 Method for Improving Performance of a Pipelined Microprocessor by Utilizing Pipeline Virtual Registers  
A method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers allows for either decreased register spillage or decreased area and power consumption of a...
US20090327663 Power Aware Retirement  
In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation...
US20090106535 SHARED PROCESSOR ARCHITECTURE APPLIED TO FUNCTIONAL STAGES CONFIGURED IN A RECEIVER SYSTEM FOR PROCESSING SIGNALS FROM DIFFERENT TRANSMITTER SYSTEMS AND METHOD THEREOF  
According to an embodiment of the present invention, a shared processor architecture in a receiver system is disclosed. The receiver system is configured to have a first functional stage and a...
US20080162894 STRUCTURE FOR A CASCADED DELAYED EXECUTION PIPELINE  
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided for improved techniques for executing instructions in a pipelined...