Matches 1 - 40 out of 40


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US20110185158 HISTORY AND ALIGNMENT BASED CRACKING FOR STORE MULTIPLE INSTRUCTIONS FOR OPTIMIZING OPERAND STORE COMPARE PENALTIES  
Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the...
US20110202747 INSTRUCTION LENGTH BASED CRACKING FOR INSTRUCTION OF VARIABLE LENGTH STORAGE OPERANDS  
A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one...
US20090063818 Alignment of Cache Fetch Return Data Relative to a Thread  
A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting...
US20070260851 Sleep optimization based on system information block scheduling  
Methods and apparatuses are presented for sleep optimization based on system information block SIB scheduling. A method for invoking sleep states within user equipment (UE) is presented. The...
US20140025928 PREDICTING REGISTER PAIRS  
Embodiments relate to reducing a number of read ports for register pairs. An aspect includes executing an instruction. The instruction identifies a pair of registers as containing a wide operand...
US20110252220 INSTRUCTION CRACKING AND ISSUE SHORTENING BASED ON INSTRUCTION BASE FIELDS, INDEX FIELDS, OPERAND FIELDS, AND VARIOUS OTHER INSTRUCTION TEXT BITS  
A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is...
US20140025929 MANAGING REGISTER PAIRING  
Embodiments relate to reducing a number of read ports for register pairs. An aspect includes maintaining an active pairing indicator that is configured to have a first value or a second value. The...
US20150039858 REDUCING REGISTER READ PORTS FOR REGISTER PAIRS  
Embodiments relate to reducing a number of read ports for register pairs. An aspect includes executing an instruction. The instruction identifies a pair of registers as containing a wide operand...
US20140025927 REDUCING REGISTER READ PORTS FOR REGISTER PAIRS  
Embodiments relate to reducing a number of read ports for register pairs. An aspect includes executing an instruction. The instruction identifies a pair of registers as containing a wide operand...
US20080028189 Microprocessor and Method of Instruction Alignment  
Therefore, a microprocessor for processing instructions is provided. Said microprocessor comprises a cache for caching instructions and/or data to be processed, which are arranged in cache words,...
US20080162879 Methods and apparatuses for aligning and/or executing instructions  
In some embodiments, a method includes receiving a sequence of instructions in a processing system, determining whether an instruction in the sequence is a type to be aligned, and if the...
US20090300328 Aligning Protocol Data Units  
An apparatus for receiving one or more protocol data units (PDUs) from a word aligned queue including a media access control (MAC) physical-layer (PHY) coprocessor (MPC) logically residing between...
US20100050026 PIPELINE OPERATION PROCESSOR AND CONTROL SYSTEM  
A pipeline operation processor comprises a pipeline processing unit and an instruction insertion controller which inserts an instruction when access to an operation memory is requested, and...
US20080140992 PERFORMING ENDIAN CONVERSION  
A computing system may support an endian toggle register (ETR) and the endianess of the endian toggle register may be designated using a set endian bit (SEB) or a clear endian bit (CEB)...
US20090182982 Rotate Then Insert Selected Bits Facility and Instructions Therefore  
A rotate then operate instruction having a Z bit is fetched and executed wherein a first operand in a first register is rotated by an amount. If the Z bit is ‘0’ the selected portion of the result...
US20090182981 Rotate Then Operate on Selected Bits Facility and Instructions Therefore  
A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected...
US20080040576 Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set  
In a variable-length instruction set wherein the length of each instruction is a multiple of a minimum instruction length granularity, an indication of the last granularity (i.e., the end) of a...
US20060155961 Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor  
Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A...
US20130305016 PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
US20130305015 PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
US20090249032 INFORMATION APPARATUS  
An information apparatus comprises: a barrel shifter composed of a bidirectional 1-bit shifter, . . . , and a bidirectional 24-bit shifter which are connected in series; a control unit for...
US20090037694 Load Misaligned Vector with Permute and Mask Insert  
Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By...
US20120079240 Reduced-Level Shift Overflow Detection  
A processor includes a shift overflow detector for rapidly detecting overflows that may result during execution of a shift instruction. Shift indication signals are generated in response to...
US20050149696 Method and apparatus to control steering of instruction streams  
Rather than steering one macroinstruction at a time to decode logic in a processor, multiple macroinstructions may be steered at any given time. In one embodiment, a pointer calculation unit...
US20130246738 INSTRUCTION TO LOAD DATA UP TO A SPECIFIED MEMORY BOUNDARY INDICATED BY THE INSTRUCTION  
A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be...
US20130246739 COPYING CHARACTER DATA HAVING A TERMINATION CHARACTER FROM ONE MEMORY LOCATION TO ANOTHER  
Copying characters of a set of terminated character data from one memory location to another memory location using parallel processing and without causing unwarranted exceptions. The character...
US20130275718 SHUFFLE PATTERN GENERATING CIRCUIT, PROCESSOR, SHUFFLE PATTERN GENERATING METHOD, AND INSTRUCTION SEQUENCE  
Based on an input index sequence (702) composed of four indices (each having a bit width of 8 bits), a shift-copier generates an index sequence (902) by shifting each index leftward by 1 bit and...
US20120254588 SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK  
Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data...
US20100211760 APPARATUS AND METHOD FOR PROVIDING INSTRUCTION FOR HETEROGENEOUS PROCESSOR  
Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands...
US20100138635 Systems and Methods for Managing Endian Mode of a Device  
Systems, methods, and devices for managing endian-ness are disclosed. In one embodiment, a device is configured to selectively operate in one of a big-endian operating mode or a little-endian...
US20150032995 PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT  
Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch...
US20140095830 INSTRUCTION FOR SHIFTING BITS LEFT WITH PULLING ONES INTO LESS SIGNIFICANT BITS  
A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data...
US20140013082 RECONFIGURABLE DEVICE FOR REPOSITIONING DATA WITHIN A DATA WORD  
Disclosed is a system and device and related methods for data manipulation, especially for SIMD operations such as permute, shift, and rotate. An apparatus includes a permute section that...
US20130275719 PACKED DATA OPERATION MASK SHIFT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS  
A method of an aspect includes receiving a packed data operation mask shift instruction. The packed data operation mask shift instruction indicates a source having a packed data operation mask,...
US20130246740 INSTRUCTION TO LOAD DATA UP TO A DYNAMICALLY DETERMINED MEMORY BOUNDARY  
A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is...
US20130205115 USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES  
Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution...
US20130159672 Bitstream Buffer Manipulation With A SIMD Merge Instruction  
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data...
US20120254589 SYSTEM, APPARATUS, AND METHOD FOR ALIGNING REGISTERS  
Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the...
US20120083912 ARITHMETIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR  
An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a...
US20110191569 DATA PROCESSING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is...

Matches 1 - 40 out of 40