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US20120290816 Optimized Scalar Promotion with Load and Splat SIMD Instructions  
Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an...
US20130262820 EVENT LOGGER FOR JUST-IN-TIME STATIC TRANSLATION SYSTEM  
Systems and methods for event logging in a just-in-time static translation system are disclosed. One method includes executing a workload in a computing system having a native instruction set...
US20120260067 MICROPROCESSOR THAT PERFORMS X86 ISA AND ARM ISA MACHINE LANGUAGE PROGRAM INSTRUCTIONS BY HARDWARE TRANSLATION INTO MICROINSTRUCTIONS EXECUTED BY COMMON EXECUTION PIPELINE  
A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner...
US20110185157 MULTIFUNCTION HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
US20140108768 Computer instructions for Activating and Deactivating Operands  
An instruction set architecture (ISA) includes instructions for selectively indicating last-use architected operands having values that will not be accessed again, wherein architected operands are...
US20090204790 BUFFER MANAGEMENT FOR REAL-TIME STREAMING  
Technologies are described herein for buffer management during real-time streaming. A video frame buffer stores video frames generated by a real-time streaming video capture device. New video...
US20090125704 DESIGN STRUCTURE FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS  
A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an...
US20120110305 Register Renamer that Handles Multiple Register Sizes Aliased to the Same Storage Locations  
A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a...
US20130145121 DYNAMICALLY CONFIGURABLE PLACEMENT ENGINE  
A stream application may allocate processing elements to one or more compute nodes (or hosts) to achieve a desired optimization goal. Each optimization mode may define processing element selection...
US20130159668 PREDECODE LOGIC FOR AUTOVECTORIZING SCALAR INSTRUCTIONS IN AN INSTRUCTION BUFFER  
A circuit arrangement, method, and program product for substituting a plurality of scalar instructions in an instruction stream with a functionally equivalent vector instruction for execution by a...
US20090182979 Computer Configuration Virtual Topology Discovery and Instruction Therefore  
In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest...
US20080022070 Programmable image readout sequencer  
A programmable sequencer for a solid-state image sensor provides hard/soft configurable control of imaging operations in an imaging core.
US20110264891 MICROPROCESSOR THAT FUSES MOV/ALU/JCC INSTRUCTIONS  
A microprocessor receives first, second, and third program-adjacent macroinstructions. The first macroinstruction moves a first operand to a first register from a second register. The second...
US20100299497 APPARATUS FOR EFFICIENTLY DETERMINING INSTRUCTION LENGTH WITHIN A STREAM OF X86 INSTRUCTION BYTES  
An apparatus efficiently determines the length of an instruction within a stream of instruction bytes processed by a microprocessor having a variable instruction length instruction set...
US20120260068 APPARATUS AND METHOD FOR HANDLING OF MODIFIED IMMEDIATE CONSTANT DURING INSTRUCTION TRANSLATION  
An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a...
US20140281386 CHAINING BETWEEN EXPOSED VECTOR PIPELINES  
Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second...
US20090030668 SIGNED/UNSIGNED INTEGER GUEST COMPARE INSTRUCTIONS USING UNSIGNED HOST COMPARE INSTRUCTIONS FOR PRECISE ARCHITECTURE EMULATION  
Architecture for efficient translation and processing of PowerPC guest instructions on an x86 host machine. In an x86-based architecture, signed integer values are projected into the unsigned...
US20070186016 DEVICE FOR TRANSFERRING DATA ARRAYS BETWEEN BUSES AND SYSTEM FOR MAC LAYER PROCESSING COMPRISING SAID DEVICE  
A device for transferring data arrays between at least two buses, the device comprising storage means for storing at least one data array, a first input/output interface for transferring data...
US20070113049 Electronic circuit with a fifo pipeline  
An asynchronously operated FIFO pipe-line (10a-d) comprises a plurality of handshake chains functionally in parallel. Successive data items are each passed by selecting a chain dependent on a...
US20130332703 Shared Register Pool For A Multithreaded Microprocessor  
A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a...
US20120084533 Efficient Parallel Floating Point Exception Handling In A Processor  
Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical...
US20090138677 System for Native Code Execution  
A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the...
US20130219150 Parsing Data Representative of a Hardware Design into Commands of a Hardware Design Environment  
A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware...
US20060242385 Dynamically reconfigurable processor  
Disclosed is a technology of generating an instruction set architecture (hereinafter, referred to as ‘ISA’) and a series of logic circuit configuration information of a processor for executing an...
US20130067199 CONTROL REGISTER MAPPING IN HETEROGENEOUS INSTRUCTION SET ARCHITECTURE PROCESSOR  
A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor...
US20100082944 Multi-thread processor  
In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread...
US20060026390 Storing contexts for thread switching  
An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after...
US20070124564 System and method for providing an extended platform for an operating system  
A system and method of adding programming to a Symbian operating system. A binary component for use by the operating system, with the binary component including both a capability level and a trust...
US20060218377 Instruction with dual-use source providing both an operand value and a control value  
A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may...
US20110099353 System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register  
Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register...
US20120144162 SYSTEMS AND METHODS FOR DETERMINING COMPUTE KERNELS FOR AN APPLICATION IN A PARALLEL-PROCESSING COMPUTER SYSTEM  
A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the...
US20060206690 MAXQ microcontroller  
A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one...
US20070300048 System and method for targeting commands to concurrent computing units executing a concurrent computing process  
A graphical user interface for a concurrent computing environment that conveys the concurrent nature of a computing environment and allows a user to monitor the status of a concurrent process...
US20080148014 METHOD AND SYSTEM FOR PROVIDING A RESPONSE TO A USER INSTRUCTION IN ACCORDANCE WITH A PROCESS SPECIFIED IN A HIGH LEVEL SERVICE DESCRIPTION LANGUAGE  
A method, system, and computer program product for providing a response to a user instruction in accordance with a process specified in a high level service description language. A method in...
US20070143579 Integrated data processor  
An integrated data processor of the present invention integrates a plurality of functions of a digital signal processor (DSP) and a microprocessor control unit (MCU). A plurality of novel...
US20060026389 Method for providing scratch registers for use by a virtual-machine monitor  
In one embodiment of the present invention, a virtual-machine monitor detects entry and exit from guest-operating system code, storing the values of a set of high-order floating point registers in...
US20110239036 WAVE PIPELINE WITH SELECTIVELY OPAQUE REGISTER STAGES  
A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal...
US20100299498 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD  
An information processing apparatus includes: a first pipeline having first nodes, and moving data held in each first node to a first node located in a first direction; a second pipeline having...
US20130191614 PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION  
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a...
US20120166765 PREDICTING BRANCHES FOR VECTOR PARTITIONING LOOPS WHEN PROCESSING VECTOR INSTRUCTIONS  
While fetching the instructions from a loop in program code, a processor calculates a number of times that a backward-branching instruction at the end of the loop will actually be taken when the...
US20060230257 System and method of using a predicate value to access a register file  
A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number...
US20070157005 Copy program and recording medium in which the copy program is recorded  
This invention provides a copy program by which the data such as static image data or moving image data, music data, can be successively copied in a recording means such as a recording medium, by...
US20070011437 System and method for pipelet processing of data sets  
The present invention is directed towards systems and methods for decomposing a complex problem or task into one or more constituent components, operating in parallel over a plurality of computing...
US20120179895 METHOD AND APPARATUS FOR FAST DECODING AND ENHANCING EXECUTION SPEED OF AN INSTRUCTION  
Method and apparatus for fast decoding of microinstructions are disclosed. An integrated circuit is disclosed wherein microinstructions are queued for execution in an execution unit having...
US20060265571 Processor with different types of control units for jointly used resources  
The invention relates to a processor comprising several control units and functional blocks which can be commonly accessed by the control units. The processor also includes a central control unit...
US20090177866 SYSTEM AND METHOD FOR FUNCTIONALLY REDUNDANT COMPUTING SYSTEM HAVING A CONFIGURABLE DELAY BETWEEN LOGICALLY SYNCHRONIZED PROCESSORS  
A method of operating a computer system. A first processor sends a first unit of binary information to an input/output (I/O) unit. The I/O unit then conveys the first unit of binary information to...
US20080028188 TIME DE-INTERLEAVER IMPLEMENTATION USING SDRAM IN A TDS-OFDM RECEIVER  
A receiver having an apparatus having a processor for processing interleaved data; and an independent memory coupled to the processor for processing the interleaved data is provided.
US20120198208 SHARED FUNCTION MULTI-PORTED ROM APPARATUS AND METHOD  
Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array...
US20110185156 EXECUTING WATCHPOINT EVENTS FOR DEBUGGING IN A "BREAK BEFORE MAKE" MANNER  
A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the...
US20130159665 SPECIALIZED VECTOR INSTRUCTION AND DATAPATH FOR MATRIX MULTIPLICATION  
A data processing element includes an input unit configured to provide instructions for scalar, vector and array processing, and a scalar processing unit configured to provide a scalar pipeline...

Matches 1 - 50 out of 89 1 2 >