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US20130339658 MANAGING PAGE TABLE ENTRIES  
A method includes identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second page...
US20120331265 Apparatus and Method for Accelerated Hardware Page Table Walk  
A method of walking page tables includes comparing a virtual address to a plurality of virtual address bit segments to identify a match. Each virtual address bit segment is associated with a page...
US20130262798 VIRTUALIZATION SYSTEM USING HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE  
One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking...
US20100318762 Synchronizing A Translation Lookaside Buffer with Page Tables  
The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping...
US20120173842 Operating System Management of Address-Translation-Related Data Structures and Hardware Lookasides  
An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the...
US20110125983 Processing System Implementing Variable Page Size Memory Organization Using a Multiple Page Per Entry Translation Lookaside Buffer  
A processing system includes a page table including a plurality of page table entries. Each of the plurality of page table entries includes information for translating a virtual address page to a...
US20130117531 METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION  
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each...
US20110179490 Apparatus and Method for Detecting a Code Injection Attack  
A code injection attack detecting apparatus and method are provided. The code injection attack may be detected based on characteristics occurring when a malicious code injected by the code...
US20130339656 Compare and Replace DAT Table Entry  
A first and a second operand are compared. If they are equal, the contents of register R1+1 are stored at the second-operand location, and the specified CPU or CPUs in the configuration are...
US20110153955 SOFTWARE ASSISTED TRANSLATION LOOKASIDE BUFFER SEARCH MECHANISM  
A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry...
US20110153949 DELAYED REPLACEMENT OF CACHE ENTRIES  
A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry...
US20120117356 Invalidating a Range of Two ro More Translation Table Entries and Instruction Therefore  
An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation,...
US20100106930 OPPORTUNISTIC PAGE LARGIFICATION  
Page tables in the last level of a hierarchical page table system are scanned for candidate page tables. Candidate page tables are converted to large pages, having a page table entry in a level...
US20140181461 REPORTING ACCESS AND DIRTY PAGES  
A method and apparatus for reporting events into at least one event log are presented. An “access” event entry may be added to an event log stored in memory when a peripheral device accesses an...
US20120265963 LARGE-PAGE OPTIMIZATION IN VIRTUAL MEMORY PAGING SYSTEMS  
A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table...
US20140156968 FLEXIBLE PAGE SIZES FOR VIRTUAL MEMORY  
A method for translating a virtual memory address into a physical memory address includes parsing the virtual memory address into a page directory entry offset, a page table entry offset, and an...
US20130339659 MANAGING ACCESSING PAGE TABLE ENTRIES  
A method for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an...
US20100250895 HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE WITH GUEST PAGE MAPPINGS  
Some embodiments of the present invention include an execution unit of a processor and a memory management unit interposed between the execution unit and an interface to memory suitable for...
US20130173882 INSTRUCTION FETCH TRANSLATION LOOKASIDE BUFFER MANAGEMENT TO SUPPORT HOST AND GUEST O/S TRANSLATIONS  
A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page...
US20100332788 AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION  
In one embodiment, the present invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, the page fault handler to determine if a page fault...
US20110138149 PREVENTING DUPLICATE ENTRIES IN A NON-BLOCKING TLB STRUCTURE THAT SUPPORTS MULTIPLE PAGE SIZES  
One embodiment provides a system that prevents duplicate entries in a non-blocking TLB that supports multiple page sizes and speculative execution. During operation, after a request for...
US20130227248 SYSTEM AND METHOD FOR SUPPORTING FINER-GRAINED COPY-ON-WRITE PAGE SIZES  
In a computer system having virtual machines, one or more unused bits of a guest virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a...
US20110022819 INDEX CACHE TREE  
Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some...
US20130024648 TLB EXCLUSION RANGE  
A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises...
US20110173411 TLB EXCLUSION RANGE  
A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises...
US20110276778 EFFICIENT SUPPORT OF MULTIPLE PAGE SIZE SEGMENTS  
An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported...
US20140168227 SYSTEM AND METHOD FOR VERSIONING BUFFER STATES AND GRAPHICS PROCESSING UNIT INCORPORATING THE SAME  
A system and method for versioning states of a buffer. In one embodiment, the system includes: (1) a page table lookup and coalesce circuit operable to provide a page table directory request for a...
US20110296136 Locking Entries Into Translation Lookaside Buffers  
Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside...
US20140122830 Operational Efficiency of Virtual TLBs  
Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in...
US20130036291 GENERATING MULTIPLE ADDRESS SPACE IDENTIFIERS PER VIRTUAL MACHINE TO SWITCH BETWEEN PROTECTED MICRO-CONTEXTS  
Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes...
US20110010521 TLB Prefetching  
In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB...
US20110202724 IOMMU Architected TLB Support  
Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and...
US20130262815 HYBRID ADDRESS TRANSLATION  
Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space....
US20120084488 Dynamic Address Translation With Translation Exception Qualifier  
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of...
US20140201494 OVERLAP CHECKING FOR A TRANSLATION LOOKASIDE BUFFER (TLB)  
An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry...
US20140101408 ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS  
An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation...
US20140101359 ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS  
An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation...
US20140181459 SPECULATIVE ADDRESSING USING A VIRTUAL ADDRESS-TO-PHYSICAL ADDRESS PAGE CROSSING BUFFER  
A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine...
US20090187730 MAINFRAME STORAGE CONTROLLER AND MAINFRAME VOLUME VIRTUALIZATION METHOD  
A storage controller of the present invention is capable of providing a plurality of external volumes to a mainframe as a single virtual volume without lowering write performance. A virtual volume...
US20140101407 SELECTABLE ADDRESS TRANSLATION MECHANISMS  
An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation...
US20140059321 Load Page Table Entry Address Instruction Execution Based on an Address Tralsnation Format Control Field  
What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode...
US20150039850 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
US20130054935 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE  
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of...
US20140173244 FILTERING REQUESTS FOR A TRANSLATION LOOKASIDE BUFFER  
The present application describes a method and apparatus for filtering requests to a translation lookaside buffer (TLB). Some embodiments of the method include receiving, from a first translation...
US20130031332 MULTI-CORE SHARED PAGE MISS HANDLER  
Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method...
US20130238874 SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER  
Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss...
US20130141446 Method and Apparatus for Servicing Page Fault Exceptions  
A method, apparatus and computer readable media for servicing page fault exceptions in a accelerated processing device (APD). A page fault related to a wavefront is detected. A fault handling...
US20090089518 SOLID STATE STORAGE RECLAMATION APPARATUS AND METHOD  
A method and apparatus are disclosed for reclaiming solid state storage with limited write cycles such as flash memory. Through the use of shared storage for common data patterns, physical space...
US20110022780 RESTORE INDEX PAGE  
Techniques for restoring index pages stored in non-volatile memory are disclosed where the index pages map logical sectors into physical pages. Additional data structures in volatile and...
US20110107057 ADDRESS TRANSLATION UNIT WITH MULTIPLE VIRTUAL QUEUES  
An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store...