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US20150052309 COMBINING ASSOCIATIVITY AND CUCKOO HASHING  
Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash...
US20130151781 Cache Implementing Multiple Replacement Policies  
In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in...
US20110010502 Cache Implementing Multiple Replacement Policies  
In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in...
US20120042126 METHOD FOR CONCURRENT FLUSH OF L1 AND L2 CACHES  
The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a...
US20050160228 Equipment and method for cache replacement  
A cache replacement equipment encompasses a cache tag table having a plurality of ways, a thread comparator connected to the cache tag table configured to compare a first thread number stored in...
US20110055485 EFFICIENT PSEUDO-LRU FOR COLLIDING ACCESSES  
An apparatus for allocating entries in a set associative cache memory includes an array that provides a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request...
US20090125684 Timer Device For Monitoring Expiration Of Products  
A timer device adapted to monitor time periods associated with foods and other substances which may have a finite time during which they are suitable e for use, comprising a timer unit (8) capable...
US20140189244 SUPPRESSION OF REDUNDANT CACHE STATUS UPDATES  
A cache management system employs a replacement policy in a manner that manages redundant accesses to cache elements. The cache management system comprises a cache, a replacement policy state...
US20130297879 PROBABILISTIC ASSOCIATIVE CACHE  
A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for...
US20140149671 PERSISTENT CACHEABLE HIGH VOLUME MANUFACTURING (HVM) INITIALIZATION CODE  
A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a...
US20110066810 PERSISTENT CACHEABLE HIGH VOLUME MANUFACTURING (HVM) INITIALIZATION CODE  
A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a...
US20090006757 HIERARCHICAL CACHE TAG ARCHITECTURE  
An apparatus, system, and method are disclosed. In one embodiment, the apparatus includes a cache memory coupled to a processor. The apparatus additionally includes a tag storage structure that is...
US20110040940 Dynamic cache sharing based on power state  
The present invention discloses a method comprising: sending cache request; monitoring power state; comparing said power state; allocating cache resources; filling cache; updating said power...
US20150143050 REUSE OF DIRECTORY ENTRIES FOR HOLDING STATE INFORMATION  
The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as...
US20110138127 AUTOMATIC DETECTION OF STRESS CONDITION  
A stress of a computerized system may be detected based on actions performed by the computerized system in respect to a storage system, such as comprising a secondary storage. The stress detection...
US20130097385 DUAL-GRANULARITY STATE TRACKING FOR DIRECTORY-BASED CACHE COHERENCE  
A system and method of providing directory cache coherence are disclosed. The system and method may include tracking the coherence state of at least one cache block contained within a region using...
US20130024620 METHOD AND APPARATUS FOR ADAPTIVE CACHE FRAME LOCKING AND UNLOCKING  
Most recently accessed frames are locked in a cache memory. The most recently accessed frames are likely to be accessed by a task again in the near future and may be locked at the beginning of a...
US20150052310 CACHE DEVICE AND CONTROL METHOD THEREOF  
A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways...
US20130275683 Programmably Partitioning Caches  
Agents may be assigned to discrete portions of a cache. In some cases, more than one agent may be assigned to the same cache portion. The size of the portion, the assignment of agents to the...
US20090327611 DOMAIN-BASED CACHE MANAGEMENT, INCLUDING DOMAIN EVENT BASED PRIORITY DEMOTION  
Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such...
US20100299482 METHOD AND APPARATUS FOR DETERMINING CACHE STORAGE LOCATIONS BASED ON LATENCY REQUIREMENTS  
A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a...
US20140089590 SYSTEM CACHE WITH COARSE GRAIN POWER MANAGEMENT  
Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache...
US20120110266 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS  
Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache...
US20100030970 Adaptive Spill-Receive Mechanism for Lateral Caches  
Improving cache performance in a data processing system is provided. A cache controller monitors a counter associated with a cache. The cache controller determines whether the counter indicates...
US20140297959 ADVANCED COARSE-GRAINED CACHE POWER MANAGEMENT  
Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other...
US20110078382 Adaptive Linesize in a Cache  
A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss...
US20060259694 BYPASSING CACHE INFORMATION  
An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from...
US20140189243 SECTORED CACHE WITH HYBRID LINE GRANULARITY  
A coarse-grained cache line may be associated with a way from a set in a cache. A first sector of the coarse-grained cache line may be stored in the way. The coarse-grained cache line may include...
US20120272007 CACHE MEMORY WITH DYNAMIC LOCKSTEP SUPPORT  
Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution...
US20060015689 Implementation and management of moveable buffers in cache system  
The present invention provides parallel processing of write-back and reload operations in a cache system and optimum circuit utilisation by implementing moveable buffers in a cache storage....
US20100049912 DATA CACHE WAY PREDICTION  
A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic...
US20060259692 WRITING TO A SPECIFIED CACHE  
An information carrier medium containing software that, when executed by a processor, causes the processor to receive input from a user of the software, the input comprising data and a cache...
US20100011165 CACHE MANAGEMENT SYSTEMS AND METHODS  
A multi mode cache system that uses a direct mapped cache scheme for some addresses and an associative cache scheme for other addresses.
US20080313406 METHODS AND SYSTEMS FOR PORTING SYSPROF  
Embodiments of the present invention provide a system profiler that can be used on any processor architecture. In particular, instead of copying an entire stack every time, the stack is divided...
US20090172289 CACHE MEMORY HAVING SECTOR FUNCTION  
A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to...
US20150026406 SIZE ADJUSTING CACHES BY WAY  
A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number...
US20070011406 Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries  
Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a...
US20080052467 System for restricted cache access during information transfers and method thereof  
Instructions involving a relatively significant information transfer or a particular type of information transfer via a cache, or specified address ranges within cache causing a cache miss result...
US20100023697 Testing Real Page Number Bits in a Cache Directory  
Testing real page number bits in a cache directory is provided. A specification of a cache to be tested is retrieved in order to test the real page number bits of the cache directory associated...
US20110296112 Reducing Energy Consumption of Set Associative Caches by Reducing Checked Ways of the Set Association  
Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are...
US20110055482 SHARED CACHE RESERVATION  
Various example embodiments are disclosed. According to an example embodiment, a shared cache may be configured to determine whether a word requested by one of the L1 caches is currently stored in...
US20150212947 DYNAMIC CACHE ENLARGING BY COUNTING EVICTIONS  
A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of...
US20120198171 Cache Pre-Allocation of Ways for Pipelined Allocate Requests  
This invention is a data processing system with a data cache. The cache controller responds to a cache miss requiring allocation by pre-allocating a way in the set to an allocation request...
US20080222361 PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS  
A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without...
US20150089143 Method and Apparatus for Saving Power by Efficiently Disabling Ways for a Set-Associative Cache  
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and...
US20120284462 METHOD AND APPARATUS FOR SAVING POWER BY EFFICIENTLY DISABLING WAYS FOR A SET-ASSOCIATIVE CACHE  
A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and...
US20070150657 Performance prioritization in multi-threaded processors  
According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority...
US20140095794 Apparatus and Method For Reducing The Flushing Time Of A Cache  
A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes...
US20140006714 SCALABLE COHERENCE FOR MULTI-CORE PROCESSORS  
An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with...
US20070033318 Alias management within a virtually indexed and physically tagged cache memory  
A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12...

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