Matches 1 - 50 out of 398 1 2 3 4 5 6 7 8 >


Match Document Document Title
US20140173209 Presenting Enclosure Cache As Local Cache In An Enclosure Attached Server  
Presenting enclosure cache as local cache in an enclosure attached server, including: determining, by the enclosure, a cache hit rate for local server cache in each of a plurality of enclosure...
US20080250206 STRUCTURE FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS  
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction(s) cache in which some lines may...
US20110231849 Optimizing Workflow Engines  
Techniques for implementing a workflow are provided. The techniques include merging a workflow to create a virtual graph, wherein the workflow comprises two or more directed acyclic graphs (DAGs),...
US20080250205 STRUCTURE FOR SUPPORTING SIMULTANEOUS STORAGE OF TRACE AND STANDARD CACHE LINES  
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may...
US20120117327 Bimodal Branch Predictor Encoded in a Branch Instruction  
Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the...
US20110153307 Transitioning From Source Instruction Set Architecture (ISA) Code To Translated Code In A Partial Emulation Environment  
In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation...
US20140201450 Optimized Matrix and Vector Operations In Instruction Limited Algorithms That Perform EOS Calculations  
There is provided a system and method for optimizing matrix and vector calculations in instruction limited algorithms that perform EOS calculations. The method includes dividing each matrix...
US20110320771 INSTRUCTION UNIT WITH INSTRUCTION BUFFER PIPELINE BYPASS  
A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the...
US20150019814 Extract Target Cache Attribute Facility and Instruction Therefore  
A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or...
US20150058573 OPERAND CACHE DESIGN  
Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and...
US20110320722 MANAGEMENT OF MULTIPURPOSE COMMAND QUEUES IN A MULTILEVEL CACHE HIERARCHY  
An apparatus for controlling access to a pipeline includes a plurality of command queues including a first subset of the plurality of command queues being assigned processes the commands of first...
US20120066483 Computing Device with Asynchronous Auxiliary Execution Unit  
A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured...
US20150052308 PRIORITIZED CONFLICT HANDLING IN A SYSTEM  
A controller has a cache to store data associated with an address that is subject to conflict resolution. A conflict resolution queue stores information relating to plural transactions, and logic...
US20110154000 Adaptive optimized compare-exchange operation  
A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange...
US20150058571 HINT VALUES FOR USE WITH AN OPERAND CACHE  
Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and...
US20110055529 EFFICIENT BRANCH TARGET ADDRESS CACHE ENTRY REPLACEMENT  
A microprocessor includes a branch target address cache (BTAC), each entry thereof configured to store branch prediction information for at most N branch instructions. An execution unit executes a...
US20140223101 REGISTER FILE HAVING A PLURALITY OF SUB-REGISTER FILES  
Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated...
US20120272006 DYNAMIC LOCKSTEP CACHE MEMORY REPLACEMENT LOGIC  
To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or...
US20150261687 EXTENDED PAGE TABLE FOR I/O ADDRESS TRANSLATION  
Embodiments are directed to a method and a computer program product for extending a page table. In an embodiment, the method comprises receiving, by a host bridge, a request. The method further...
US20140189242 LOGGING IN SECURE ENCLAVES  
Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an...
US20140229677 HIDING INSTRUCTION CACHE MISS LATENCY BY RUNNING TAG LOOKUPS AHEAD OF THE INSTRUCTION ACCESSES  
This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes)...
US20130290640 BRANCH PREDICTION POWER REDUCTION  
In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the...
US20090204764 Cache Pooling for Computing Systems  
In a computing system a method and apparatus for cache pooling is introduced. Threads are assigned priorities based on the criticality of their tasks. The most critical threads are assigned to...
US20110153988 METHODS AND APPARATUS TO PERFORM ADAPTIVE PRE-FETCH OPERATIONS IN MANAGED RUNTIME ENVIRONMENTS  
Methods and apparatus to perform adaptive pre-fetch operations in managed runtime environments are disclosed herein. An example pre-fetch unit for use with a pre-fetch operation includes a first...
US20090265507 SYSTEM TO REDUCE DRIVE OVERHEAD USING A MIRRORED CACHE VOLUME IN A STORAGE ARRAY  
A system comprising a host, a solid state device, and an abstract layer. The host may be configured to generate a plurality of input/output (IO) requests. The solid state device may comprise a...
US20120198169 Binary Rewriting in Software Instruction Cache  
Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target...
US20110320785 Binary Rewriting in Software Instruction Cache  
Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target...
US20070067572 Buffering missed requests in processor caches  
The present disclosure relates to caches that are capable of improving processor performance. In some embodiments, among others, a cache request is received, and logic within the cache determines...
US20090063773 Technique to enable store forwarding during long latency instruction execution  
A technique to allow independent loads to be satisfied during high-latency instruction processing. Embodiments of the invention relate to a technique in which a storage structure is used to hold...
US20100318569 POPULATING A CACHE SYSTEM BASED ON PRIVILEGES  
A cache system is updated upon determining that a current privilege has not been checked for the session. Updating the cache system includes receiving all data items that are accessible for the...
US20120072700 MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS  
A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a...
US20070067573 THREAD-SHARED SOFTWARE CODE CACHES  
A runtime system using thread-shared code caches is provided which avoids brute-force all-thread-suspension and monolithic global locks. In one embodiment, medium-grained runtime system...
US20130262771 INDICATING A LENGTH OF AN INSTRUCTION OF A VARIABLE LENGTH INSTRUCTION SET  
Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of...
US20110161575 MICROCODE REFACTORING AND CACHING  
Methods and apparatus relating to microcode refactoring and/or caching are described. In some embodiments, an off-chip structure that stores microcode is shared by multiple processor cores. Other...
US20090172285 TRACKING TEMPORAL USE ASSOCIATED WITH CACHE EVICTIONS  
A method and apparatus for tracking temporal use associated with cache evictions to reduce allocations in a victim cache is disclosed. Access data for a number of sets of instructions in an...
US20110035570 MICROPROCESSOR WITH ALU INTEGRATED INTO STORE UNIT  
A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and...
US20150058572 INTELLIGENT CACHING FOR AN OPERAND CACHE  
Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and...
US20080183968 COMPUTER SYSTEM HAVING CACHE SYSTEM DIRECTLY CONNECTED TO NONVOLATILE STORAGE DEVICE AND METHOD THEREOF  
A computer system includes a nonvolatile memory for storing instructions, a microprocessor, for controlling operation of the computer system, and a cache system coupled to the microprocessor and...
US20140244933 Way Lookahead  
Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set...
US20110219188 CACHE AS POINT OF COHERENCE IN MULTIPROCESSOR SYSTEM  
In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of...
US20140052921 STORE-EXCLUSIVE INSTRUCTION CONFLICT RESOLUTION  
A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20)....
US20110145802 ACCELERATING UNBOUNDED MEMORY TRANSACTIONS USING NESTED CACHE RESIDENT TRANSACTIONS  
Using cache resident transaction hardware to accelerate a software transactional memory system. The method includes identifying a plurality of atomic operations intended to be performed by a...
US20080086597 Apparatus and Method for Using Branch Prediction Heuristics for Determination of Trace Formation Readiness  
A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with...
US20100306476 CONTROLLING SIMULATION OF A MICROPROCESSOR INSTRUCTION FETCH UNIT THROUGH MANIPULATION OF INSTRUCTION ADDRESSES  
Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address...
US20060190686 Cache circuit  
In the cache circuit, an instruction cache hit counter counts the number of cache hits, and an instruction memory access counter counts the number of times of instruction access. An instruction...
US20100306474 CACHE LINE USE HISTORY BASED DONE BIT MODIFICATION TO I-CACHE REPLACEMENT SCHEME  
A method of providing history based done logic for instructions includes receiving an instruction in a cache line in a L2 cache; and loading the cache line into an L1 cache with a history count...
US20100030968 Methods of Cache Bounded Reference Counting  
A computer implemented method of cache bounded reference counting for computer languages having automated memory management in which, for example, a reference to an object ā€œZā€ initially stored in...
US20130117510 SYSTEM AND METHOD FOR MANAGING AN OBJECT CACHE  
In order to optimize efficiency of deserialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores...
US20120246408 ARITHMETIC PROCESSING DEVICE AND CONTROLLING METHOD THEREOF  
A physical process ID (PPID) is stored for each cache block of each set, and a MAX WAY number for each PPID value is stored for each of index values #1 to #n. A MAX WAY number corresponding to a...
US20110093658 CLASSIFYING AND SEGREGATING BRANCH TARGETS  
A system and method for branch prediction in a microprocessor. A branch prediction unit stores an indication of a location of a branch target instruction relative to its corresponding branch...

Matches 1 - 50 out of 398 1 2 3 4 5 6 7 8 >