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US20050216617 |
Obtaining queue measurement data for a range of logical control unit queues
I/O measurement data for channels attached to logical control unit queues is obtained related to a plurality of logical control unit queues. A store secondary queue measurement data instruction... |
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US20070067812 |
Information providing method
An information providing method distributes in advance a playback file upon downloading which is to be played in a period between the start of downloading files and the start of playing the files.... |
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US20060106959 |
DISK DRIVER CLUSTER MANAGEMENT OF TIME SHIFT BUFER WITH FILE ALLOCATION TABLE STRUCTURE
A file allocation system for a hard disk drive includes a memory with driver logic and a processor configured with the driver logic to receive a request to allocate hard disk space of a defined... |
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US20110107380 |
MEDIA DISTRIBUTION TO A PLURALITY OF DEVICES UTILIZING BUFFERED DISPERSED STORAGE
A method begins by a processing module receiving a plurality of playback requests for a stored program, wherein the stored program is stored in a dispersed storage network (DSN) memory as a... |
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US20060224789 |
Flash memories and processing systems including the same
A memory may include first and second buffer memories and a memory core. The memory core may include memory blocks each having a plurality of pages and a page buffer for reading data from a... |
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US20070214294 |
Method and System for Backing Up Storage System Data
The present invention provides a method, a system and code for backing up information on a storage system, for example, a disk system, connected to a storage area network. The host or server... |
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US20070239906 |
Input/output agent having multiple secondary ports
Embodiments of the invention are generally directed to systems, methods, and apparatuses for an input/output agent having multiple secondary ports. In some embodiments, the input/output agent... |
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US20070260778 |
MEMORY CONTROLLER WITH BI-DIRECTIONAL BUFFER FOR ACHIEVING HIGH SPEED CAPABILITY AND RELATED METHOD THEREOF
A memory controller for accessing a serial Flash memory is disclosed. The memory controller includes a logic circuit; a bi-directional buffer, coupled to the logic circuit, for selectively... |
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US20090193182 |
INFORMATION STORAGE DEVICE AND CONTROL METHOD THEREOF
According to one embodiment, an information storage device includes a non-volatile storage medium, a non-volatile memory configured to store specific data blocks to be read for a host device and... |
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US20050144341 |
Buffer management via non-data symbol processing for a point to point link
A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link.... |
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US20080010390 |
Facilitating Inter-DSP Data Communications
A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate... |
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US20080256271 |
Methods and apparatus for reducing storage usage in devices
Transmission buffer apparatus and methods configured to minimize the storage requirements for transmission/retransmission of data by allocating retransmission data to two or more types of storage.... |
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US20060129712 |
Buffer chip for a multi-rank dual inline memory module (DIMM)
The invention refers to a buffer chip for driving external input signals applied to a multi-rank dual inline memory module (DIMM) to a predetermined number (N) of memory chips mounted on a printed... |
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US20110029741 |
DATA MANAGEMENT METHOD AND MEMORY DEIVCE
The invention provides a data management method for a memory device. In one embodiment, the memory device comprises a plurality of memories for data storage. First, write data and a write logical... |
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US20150363340 |
PROVIDING MULTIPLE SYNCHRONOUS SERIAL CONSOLE SESSIONS USING DATA BUFFERING
Embodiments are directed to providing synchronous communication between a baseboard management controller (BMC) and a serial console using data buffering, and to providing multiple synchronous... |
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US20080114910 |
APPARATUS AND METHOD FOR HIGH SPEED ULTRASONIC DATA ACQUISITION
The present invention provides an apparatus and method for high-speed ultrasonic data acquisition. The apparatus is arranged within an ultrasonic detection system, and comprises: an acquisition... |
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US20100223422 |
Advanced Dynamic Disk Memory Module
Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the... |
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US20050289254 |
Dynamic buffer allocation method
A dynamic allocation method for DMA buffers. A DMA controller is directed to move data from an input/output (I/O) device to buffers linked in a buffer ring. Next, free buffers in the buffer ring... |
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US20110276731 |
DUAL-PORT FUNCTIONALITY FOR A SINGLE-PORT CELL MEMORY DEVICE
A network node (5) including a line card (20) for packet-based data communications is disclosed. The line card (20) includes a transmit FIFO buffer (24T) and a receive FIFO buffer (24R), for... |
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US20070255866 |
Method and system for a user space TCP offload engine (TOE)
Certain aspects of a method and system for user space TCP offload are disclosed. Aspects of a method may include offloading transmission control protocol (TCP) processing of received data to an... |
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US20090313399 |
DIRECT MEMORY ACCESS CHANNEL
A system and method for using a direct memory access (“DMA”) channel to reorganize data during transfer from one device to another are disclosed herein. A DMA channel includes demultiplexing logic... |
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US20070005833 |
Transmit buffers in connection-oriented interface
A connection-oriented protocol controller has a prefetch engine to obtain payload data that is destined to a remote node, before a connection is established with the remote node. A number of... |
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US20090327535 |
ADJUSTABLE READ LATENCY FOR MEMORY DEVICE IN PAGE-MODE ACCESS
A read process in a memory device is optimized. Sub-pages of a page of data are read from storage elements by an internal controller of the memory device at a read speed of the internal... |
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US20070011365 |
Electric field device
The invention relates to an electric field device (1) comprising a computer-controlled least one input/output module (3a-3f) data inputs and/or data outputs. The central control module (2) and the... |
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US20090259789 |
MULTI-PROCESSOR, DIRECT MEMORY ACCESS CONTROLLER, AND SERIAL DATA TRANSMITTING/RECEIVING APPARATUS
A CPU 5 is provided with both the functionality of issuing an external bus access request directly to an external memory interface 3 and the functionality of issuing a DMA transfer request to a... |
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US20060155894 |
Asynchronous messaging in storage area network
A computer system includes an asynchronous messaging-and-queuing system; and a storage area network having a storage area network controller in communication with the asynchronous... |
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US20070005831 |
Semiconductor memory system
The present invention relates to a semiconductor memory system including a memory controller transmitting high speed write data, command and address signal streams based on a predefined... |
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US20130111084 |
METHODS AND DEVICES FOR SINGLE LINK AGGREGATED BUSES
An load balanced interconnect between a master device and slave devices, having a buffer coupling the master to the slave devices, and queuing access requests from the master to respective ones of... |
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US20100161834 |
USER INTERFACE BETWEEN A MICROCONTROLLER AND A FLEXRAY COMMUNICATIONS MODULE; FLEXRAY USER; AND METHOD FOR TRANSMITTING MESSAGES VIA SUCH AN INTERFACE
A user interface between a FlexRay communications module which is connected to a FlexRay communications link over which messages are transmitted and which includes a message memory for buffer... |
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US20140325125 |
ATOMIC WRITE METHODS
A method of transmitting atomic write data from a host to a data storage device in a data system includes; communicating a header identifying a plurality of data chunks associated with an atomic... |
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US20100211616 |
Performance by Avoiding Disk I/O for Deduplicated File Blocks
A computer having deduplicated data stores files comprised of file blocks in a volume. File blocks are copied from the volume to memory as needed by processes. An operating system searches a... |
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US20080147915 |
Management of memory buffers for computer programs
A method and apparatus for management of memory buffers for computer programs. An embodiment of a method includes executing a computer program, the computer program including one or more threads.... |
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US20070220184 |
Latency-locked loop (LLL) circuit, buffer including the circuit, and method of adjusting a data rate
A latency locked loop (LLL) circuit for a first in first out (FIFO) buffer, includes a latency error estimator for estimating a latency error for the buffer by measuring a latency of the buffer... |
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US20070162658 |
Data transfer apparatus, storage device control apparatus and control method using storage device control apparatus
A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying... |
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US20090094391 |
STORAGE DEVICE INCLUDING WRITE BUFFER AND METHOD FOR CONTROLLING THE SAME
A storage device having a write buffer and a method of controlling the same, in which data having a relatively lower temporal and spatial locality from an input/output (I/O) operation request... |
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US20050120148 |
Storage medium storing preloading data, and apparatus and method for reproducing information from storage medium
A storage medium including image data, program data to control an interaction with a user during reproduction of the image data, and loading information to cause the image data to be seamlessly... |
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US20080162748 |
EFFICIENT POWER MANAGEMENT TECHNIQUES FOR COMPUTER SYSTEMS
Techniques involving power management techniques in computer systems are disclosed. For instance, an apparatus may include an input output queue (IOQ), an interface coupled to a processor, and a... |
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US20060242337 |
Alignment of instructions and replies across multiple devices in a cascaded system, using buffers of programmable depths
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or... |
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US20060242336 |
Alignment of instructions and replies across multiple devices in a cascaded system, using buffers of programmable depths
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or... |
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US20150278149 |
Method for Real-Time HD Video Streaming Using Legacy Commodity Hardware Over an Unreliable Network
Data to be streamed from source device to destination device is processed through a plurality of pipeline stages, each responsible for handling a different part of the overall streaming process,... |
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US20070061494 |
Semiconductor memory system, semiconductor memory chip, and method of masking write data in a semiconductor memory chip
In a semiconductor memory chips, a semiconductor memory system, and a method of masking write data, data, command, and address signal streams are serially transmitted in the form of signal frames... |
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US20070016700 |
Integrated circuit device and electronic instrument
An integrated circuit device has a data memory including a memory cell array which includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells, and a memory output... |
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US20110296124 |
PARTITIONING MEMORY FOR ACCESS BY MULTIPLE REQUESTERS
An apparatus comprising a plurality of buffers and a channel router circuit. The buffers may be each configured to generate a control signal in response to a respective one of a plurality of... |
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US20100312956 |
Load reduced memory module
A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register... |
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US20100281192 |
APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A DATA PROCESSING SYSTEM
An apparatus for transferring data between buffers within a data processing architecture includes first and second memory devices. The apparatus further includes a first connection manager... |
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US20080147916 |
DATA SYNCHRONIZATION METHOD OF DATA BUFFER DEVICE
In a data synchronization method for use in a multilane data buffer device including at least a first data buffer in a first lane and a second data buffer in a second lane, when there is a first... |
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US20080005402 |
Gals-based network-on-chip and data transfer method thereof
A GALS-based network-on-chip (NoC) includes a plurality of asynchronous first-in first-out (FIFO) input buffers connected to a plurality of IPs that asynchronously receive data; a plurality of... |
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US20060253622 |
Method and device for congestion notification in packet networks indicating several different congestion causes
A device for routing data units in a network, and a method of controlling a device for routing data units in a network, where the device 1 is capable of identifying one or more causes of... |
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US20100057953 |
DATA PROCESSING SYSTEM
There is provided a data processing system comprising at least one processing module having at least one processor processing data and a data input/output unit that classifies and buffers input... |
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US20070260777 |
Queues for information processing and methods thereof
Systems and methods implement queues that perform write operations in a re-circulating sequential manner. The nature of the queue systems of the present invention allow writes to the queue to... |