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US20080244146 AGGREGATION OF ERROR MESSAGING IN MULTIFUNCTION PCI EXPRESS DEVICES  
A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several functions share a common PCIe interface...
US20070150637 Bus systems and method for reconfiguration  
The invention relates to methods and embodiments of bus systems for configurable architectures. Special consideration is to the optimisation of configuration and reconfiguration efficiency.
US20060095637 Bus control device, arbitration device, integrated circuit device, bus control method, and arbitration method  
A bus control device for controlling a bus system composed of a first bus and a second bus connected via a bridge unit. In the bus control device, a first arbitration unit obtains bandwidth...
US20050251608 Vehicle network with interrupted shared access bus  
A vehicle network architecture includes an interrupted shared-access bus and a switch fabric incorporated therein at the point of interruption. The switch fabric permits incorporation of a feature...
US20130262733 DISTRIBUTED REORDER BUFFERS  
A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in...
US20120297106 Method and System for Dynamically Managing a Bus of a Portable Computing Device  
A method and system for dynamically managing a bus within a portable computing device (“PCD”) are described. The method and system include monitoring software requests with a bus manager. The bus...
US20090037635 BUS ARBITRATION DEVICE  
A bus arbitration device includes a top arbiter, and the hierarchical bus arbitration device also includes a first arbiter. The said first arbiter arbitrates the first kind of requests, wherein...
US20140310444 DYNAMIC BALANCING OF BUS BANDWIDTH ACROSS MULTIPLE ROUTES  
A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback...
US20060026330 Bus arbitration system that achieves power savings based on selective clock control  
A bus arbitration system includes a bus master, a bus arbitration circuit and a clock signal changing circuit. The bus master is configured to enter a power saving mode of operation in response to...
US20080320181 Hardware-Based Virtualization of BIOS, Disks, Network-Interfaces, & Consoles Using a Direct Interconnect Fabric  
A multi-computer system has many processors that share peripherals. The peripherals are virtualized by hardware without software drivers. Remote peripherals appear to the operating system to be...
US20070186026 System having bus architecture for improving CPU performance and method thereof  
A system and method for improving the performance of a central processing unit (CPU), in which the system includes a first master such as a CPU, a first local bus connected to a memory device, a...
US20140229651 MANAGING ARBITRATION IN MIXED LINK RATE WIDE PORTS  
Systems and methods presented herein provide for the management of link rates for connecting targets devices (e.g., storage devices) to initiators (e.g., host systems). In one embodiment, an...
US20100251014 COMPUTER AND FAILURE HANDLING METHOD THEREOF  
A computer system including a plurality of PCIe paths is configured such that a failed PCIe path only is disabled, thereby preventing the computer system from system resetting. The computer...
US20060218334 System and method to reduce memory latency in microprocessor systems connected with a bus  
A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message...
US20060026329 System and method for an arbiter rewind  
The rewind arbiter system provides a system and method for arbitrating a device. Briefly described, one embodiment comprises a plurality of controlled devices configured to access a shared...
US20060095634 Method and apparatus for round robin resource arbitration with a fast request to grant response  
Various methods and apparatuses are described for an arbitration unit that implements a round robin policy. Each requesting device has an equal chance of accessing a shared resource based upon a...
US20080162770 HARDWARE VOTING MECHANISM FOR ARBITRATING SCALING OF SHARED VOLTAGE DOMAIN, INTEGRATED CIRCUITS, PROCESSES AND SYSTEMS  
An electronic circuit includes processors (CPU1, CPU2) operable to make respective voltage requests (Vcpu1, Vcpu2), and a power management circuit (1470) having a controllable supply voltage...
US20090216933 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION  
A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed...
US20130275647 PCIE SMBUS SLAVE ADDRESS SELF-SELECTION  
Embodiments of the invention describe an apparatus, system and method for slave devices to “self-select” their own Inter-Integrated Circuit/System Management Bus (I2C/SMBus) slave addresses upon...
US20050223150 Resource management device, resource management system, and resource management method  
A resource request is continuously accepted within predetermined time by a resource management device that comprises a resource request accepting unit, a measuring unit, and an allocating unit....
US20090164691 IO PROCESSOR  
An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an...
US20060041705 SYSTEM AND METHOD FOR ARBITRATION BETWEEN SHARED PERIPHERAL CORE DEVICES IN SYSTEM ON CHIP ARCHITECTURES  
A system for implementing arbitration between one or more shared peripheral core devices in system on chip (SOC) integrated circuit architecture includes a first microprocessor in communication...
US20060242351 Method and apparatus for loading instructions into high memory  
There is provided a system and method for loading instructions into high memory. Specifically, there is provided a method of operating a computer comprising entering a protected mode before the...
US20140032808 INTEGRATED CIRCUIT HAVING A BUS NETWORK, AND METHOD FOR THE INTEGRATED CIRCUIT  
A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages...
US20130254449 COLLABORATIVE BUS ARBITRATION MULTIPLEX ARCHITECTURE AND METHOD OF ARBITRATION OF DATA ACCESS BASED ON THE ARCHITECTURE  
A collaborative bus arbitration multiplex architecture includes of a main memory, a bus, a plurality of BMPDs, and a BAM. Arbitration can be done according to the following steps of awaiting...
US20150067226 BACKPLANE CONTROLLER TO ARBITRATE MULTIPLEXING OF COMMUNICATION  
A backplane controller to couple to a carrier interface and a plurality of host controllers of different types. The backplane controller is to identify a host controller corresponding to a type of...
US20080034146 Systems and Methods for Transactions Between Processor and Memory  
Circuits for improving efficiency and performance of processor-memory transactions are disclosed. One such system includes a processor having a first bus interface unit and a second bus interface...
US20100005213 Access Table Lookup for Bus Bridge  
Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing....
US20080235428 METHOD AND SYSTEM FOR DYNAMIC SWITCHING BETWEEN MULTIPLEXED INTERFACES  
A bridge is disclosed. The bridge comprises a first interface having at least one multiplexed clock signal line. The multiplexed clock signal line outputs first and second control signals for...
US20090327569 CONTROLLED FREQUENCY CORE PROCESSOR AND METHOD FOR STARTING-UP SAID CORE PROCESSOR IN A PROGRAMMED MANNER  
Embodiments of the invention relate to a driven-frequency processor core. It comprises at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses...
US20110179212 Bus arbitration for sideband signals  
Systems and methods of bus arbitration for sideband signals in a multichip system are disclosed. An exemplary method comprises packaging at least one sideband signal as a micropacket. The method...
US20060161714 Method and apparatus for monitoring number of lanes between controller and PCI Express device  
After the initialization of the information processing apparatus, the MMB reads out a value in the Negotiated Link Width register and stores the value in a RAM. When receiving an interrupt from...
US20070073955 Multi-function PCI device  
A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration...
US20070220193 DATA COMMUNICATION CIRCUIT AND ARBITRATION METHOD  
A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to...
US20110185102 BUS BRIDGE AND METHOD FOR INTERFACING OUT-OF-ORDER BUS AND MULTIPLE ORDERED BUSES  
A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an...
US20060282601 Information processing apparatus and power-saving controlling method  
According to one embodiment, an information processing apparatus includes a first bridge circuit which communicates with a processor and a storage section, a second bridge circuit which...
US20120079159 Throttling Integrated Link  
Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated...
US20140215116 MULTI-BUS SYSTEM  
A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be...
US20080016265 INFORMATION PROCESSING APPARATUS AND DATA COMMUNICATION DEVICE  
An information processing apparatus includes a plurality of data communication devices via a high-speed serial bus with a plurality of traffics in different directions present between the data...
US20100211720 Crossbar circuitry and method of operation of such crossbar circuitry  
Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths...
US20100115171 MULTI-CHIP PROCESSOR  
Provided is a multiprocessor configured by stacking a plurality of unit chips each having, at least, a processor core and a memory, and the unit chip has a configuration including: a plurality of...
US20090300257 System and Method of Increasing Data Processing on a Diagnostic Tool  
A method of processing J1850 requests using a scan tool having multiple processor systems is provided. The scan tool includes a first processor that processes data according to scan tool functions...
US20170161215 PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN  
A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby...
US20170083471 SINGLE CYCLE ARBITRATION  
An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration...
US20160371203 Multiple Access Single SDIO Interface with Multiple SDIO Units  
A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input...
US20160292093 BUS SYSTEM INCLUDING BRIDGE CIRCUIT FOR CONNECTING INTERLOCK BUS AND SPLIT BUS  
A bus system is configured by connecting an unretriable interlock bus and a split bus through first and second bridge circuits and respectively connecting first and second channels of the split...
US20160232119 SHARING MEMORY BETWEEN USB Enabled Devices  
At least one Universal Serial Bus (USB) device is coupled to shared memory. The memory is accessible via the at least one USB interface wherein the memory is configured to be shared between the at...
US20160179738 METHOD, APPARATUS AND SYSTEM FOR INTEGRATING DEVICES IN A ROOT COMPLEX  
In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex...
US20160140071 Arbitrated Access To Resources Among Multiple Devices  
An arbiter circuit manages and enforces arbitration and quality of service (QOS) among multiple devices accessing a resource, such as a memory. The arbiter circuit receives requests from a number...
US20160103772 SIDE CHANNEL ACCESS THROUGH USB STREAMS  
A system may provide side channel access of a Universal Serial Bus (USB) device using USB streams. The system may include a USB interface with a USB device controller, an internal bus, a logical...

Matches 1 - 50 out of 61 1 2 >