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US20070233926 Bus width automatic adjusting method and system  
A bus width automatic adjusting method and system is proposed, which is designed for use with a computer platform for providing the computer platform with a bus width automatic adjusting function;...
US20070180179 System bus control apparatus, integrated circuit and data processing system  
The present invention provides a system bus control apparatus that effectively utilizes a system bus to the full and realizes efficient data transfer. A system bus control apparatus includes a...
US20070233930 System and method of resizing PCI Express bus widths on-demand  
A peripheral component Interconnect (PCI) switch that has at least one control logic device that is capable of changing, on-demand, widths of dedicated buses is provided. The buses are PCI Express...
US20100064089 BUS WIDTH NEGOTIATION  
There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured...
US20140006673 UTILIZATION-AWARE LOW-OVERHEAD LINK-WIDTH MODULATION FOR POWER REDUCTION IN INTERCONNECTS  
Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic...
US20050262284 Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link  
A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link...
US20070067542 Microcontroller architecture including a predefined logic area and customizable logic areas  
A microcontroller architecture in accordance with this invention provides modules or circuitry that may be programmed with a protocol for communication or other application. The architecture in...
US20070294455 Data Interface  
In order provide a host apparatus 20, such as a digital television receiver, with the capability of transmitting commands to an external storage medium device 21 connected to the host apparatus 20...
US20060218332 Interface circuit, system, and method for interfacing between buses of different widths  
Interface circuits and methods for transferring data between buses of different widths are disclosed herein. The interface circuits comprise first control logic configured to provide a selection...
US20070239922 Technique for link reconfiguration  
A technique to reconfigure a link within a common system interface (CSI) link. More particularly, embodiments described herein relate to transmitting a signal to reconfigure a link while data is...
US20080046626 Semiconductor device and BUS connecting method  
A first internal resource has a first register which is accessible from an external bus via an internal bus and has a same data width as that of the internal bus which is larger than that of the...
US20060123179 Controlling issuance of requests  
Apparatus and method are disclosed that control the issuance of posted and non-posted requests. Some embodiments maintain a specified period between successive non-posted requests on a bus. The...
US20090132748 MULTIPLE CARRIER SIGNALS ON A LEGACY BUS  
A device (e.g., an ultra-wideband device) is added to a system including a legacy wired bus (e.g., a MIL-STD 1553 bus). The legacy bus has a legacy bus signal with a center frequency, and the...
US20140351466 HOST/CLIENT SYSTEM HAVING A SCALABLE SERIAL BUS INTERFACE  
According to one exemplary embodiment, a system is provided. The system includes a system bridge, a host module including a central processing unit (CPU) coupled to the system bridge, a scalable...
US20060101184 Dual speed/dual redundant bus system  
Method and apparatus for use of the dual redundant bus network utilizing time and frequency multiplexing techniques to provide a high bit rate system that maintains a lower bit error rate with...
US20070226393 Association of Nodes Connected to a Bus System  
A bus system comprises a data bus (10), a central unit (20) and a number of input (30A-B) and output (40A-D) nodes. The system is arranged such that nodes (30A-B, 40A-D) changing their states,...
US20060248255 Interface Circuit For A Central Processing Unit  
An interface circuit for a central processing unit includes a CPU card, a slot for receiving the CPU card, and a graphics card interface coupled to the slot for transmitting signals provided by...
US20070198761 Connection management mechanism  
A host device is disclosed. The host device includes a receive frame and primitive sequence processor, a transmitter and a connection manager to open and terminate a connection with a target device.
US20070094436 System and method for thermal management in PCI express system  
The number of lanes used to communicate with a plug-in graphics card over a PCI Express bus is dynamically established based on sensed temperature in the system, to maximize the number of lanes...
US20080307145 Interconnect and a Method for Designing an Interconnect  
A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form...
US20080183937 Method and Apparatus to Reduce EMI Emissions Over Wide Port SAS Buses  
A mechanism is provided for selecting IDLE patterns based on data being transmitted on the different ports of a wide lane serial attached small computer system interface cable. The mechanism...
US20100017553 INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS  
A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the...
US20090198857 SELECTIVE BROADCASTING OF DATA IN SERIES CONNECTED DEVICES  
A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique...
US20070067541 Method and apparatus for automatically adjusting bus widths  
A method for automatically adjusting bus widths for a first slot and a second slot of a riser card according to the number of interface cards inserted to the slots. Half of the bus width for the...
US20080086577 Digital Television System, Memory Controller, and Method for Data Access  
A digital television system, a memory controller, and a method for data access are provided. The digital television system comprises a memory and the memory controller. The memory controller...
US20050283561 Method, system, and apparatus to decrease CPU temperature through I/O bus throttling  
A method, apparatus, and system are disclosed. In one embodiment the method comprises detecting a temperature event in a processor and modifying bus frequency of a bus coupled to the processor in...
US20060161698 Architecture for accessing an external memory  
Provided is an external memory accessing architecture for use with IC comprising a first bus connected to an external memory and having n-bit data width; a first buffer unit of k serially...
US20090119438 Data Processing Device Adaptable to Variable External Memory Size and Endianess  
A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external...
US20130159589 BUS CONTROL DEVICE AND BUS CONTROL METHOD  
A bus control device includes a storing unit that stores therein a threshold related to bus width of a bus that is a transfer path for data, a comparing unit that compares, when the bus width is...
US20120173850 INFORMATION PROCESSING APPARATUS  
A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small...
US20140258582 SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES  
A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses....
US20100082861 MEMORY SYSTEM AND METHOD  
In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory...
US20150032931 Synchronous Bus Width Adaptation  
A system includes a first processing component, a second processing component, and an adapted bus linking the first and second processing components. The adapted bus may account for a circuit...
US20140258581 Method and Device for Serial Data Transmission Having a Flexible Message Size and a Variable bit Length  
A method for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, the transmitted messages having a logical structure according to CAN...
US20140115221 Processor-Based System Hybrid Ring Bus Interconnects, and Related Devices, Processor-Based Systems, and Methods  
Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided....
US20100281198 Bus relay device and bus control system  
A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus...
US20100185826 ACCESS KEY GENERATING APPARATUS AND INFORMATION PROCESSING APPARATUS  
An access key generating apparatus includes: a bit field converting unit which converts a partial bit field into a reduced bit field having a bit width shorter than a bit width of the partial bit...
US20100153609 NON-SYSTEM BUS WIDTH DATA TRANSFER EXECUTABLE AT A NON-ALIGNED SYSTEM BUS ADDRESS  
Disclosed are a method and apparatus of non-system bus width data transfer executable at a non-aligned system bus address. In one embodiment, a method of a controller is described. The method...
US20170178697 DRAM DATA PATH SHARING VIA A SPLIT LOCAL DATA BUS  
Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global...
US20170154008 Dynamic Re-Allocation of Computer Bus Lanes  
The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in...
US20170154000 Dynamic Re-Allocation of Computer Bus Lanes  
The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector...
US20170109300 HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS  
An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit...
US20170010980 METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING ADDRESS DATA  
A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device, and an address bus configured to...
US20160378711 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER  
A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including...
US20160306770 ENHANCED VIRTUAL GPIO WITH MULTI-MODE MODULATION  
A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation to transmit a plurality of GPIO signals as virtual GPIO signals.
US20160306765 LOW POWER PARALLELIZATION TO MULTIPLE OUTPUT BUS WIDTHS  
A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes...
US20160291974 Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word and Non-Orthogonal Register Data File  
Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a...
US20160196231 SYSTEM AND METHOD FOR BUS BANDWIDTH MANAGEMENT IN A SYSTEM ON A CHIP  
Various embodiments of methods and systems for managing bus bandwidth allocation in a system on a chip are disclosed. Certain embodiments monitor a high speed bus for a measurement window of time...
US20160179737 PIN-CONFIGURABLE INTERNAL BUS TERMINATION SYSTEM  
A pin-configurable bus termination system may includes a bus connector attached to an end of a bus. The bus connector may be configured for electrically connecting the bus to an input connector of...
US20160170918 FAULT TOLERANT LINK WIDTH MAXIMIZATION IN A DATA BUS  
Embodiments of systems and methods for fault tolerant link width maximization in a data bus are described. Embodiments of methods may include checking a data bus connection to determine if a...

Matches 1 - 50 out of 69 1 2 >