Matches 1 - 50 out of 220 1 2 3 4 5 >


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US20120166693 Intelligent Asset Management System  
A system and method of associating the identification of a server with its physical location thorough the use of an asset management strip and asset management tags. The asset management strip is...
US20140181340 DETERMINISTIC METHOD TO SUPPORT MULTIPLE PRODUCERS WITH MULTIPLE CONSUMERS IN PEER OR HIERARCHICAL SYSTEMS  
A transaction processing method is disclosed to solve the issue of multiple producers (software and hardware) and one or more consumers operating in a peer or hierarchical system. The transaction...
US20140181339 EQUALIZATION COEFFICIENT SEARCH ALGORITHM  
A method comprises selecting a starting point on a map of equalization coefficients and measuring an eye height of a signal transmitted using the set of equalization coefficients associated with...
US20110302343 SYSTEMS AND METHODS FOR PROVIDING INSTANT-ON FUNCTIONALITY ON AN EMBEDDED CONTROLLER  
Systems and methods for providing instant-on functionality on an embedded controller are disclosed. A method of providing instant-on functionality on a controller comprises an initial state, an...
US20070101030 Bus system for integrated circuit  
A bus system is disclosed for establishing signal connections to a plurality of functional units standing in operative connection to the integrated circuit, which are designed to generate and/or...
US20110283029 IMPLEMENTING ELECTRONIC CHIP IDENTIFICATION (ECID) EXCHANGE FOR NETWORK SECURITY  
A method and circuit for implementing electronic chip identification (ECID) exchange for network security in an interconnect system, and a design structure on which the subject circuit resides are...
US20130317668 OEM Safe Aftermarket Gateway  
The OEM safe aftermarket gateway is used to enable aftermarket devices and systems that the OEM did not design or specify to be connected to the OEM vehicles without negatively affecting the...
US20120017213 ULTRA-LOW COST SANDBOXING FOR APPLICATION APPLIANCES  
The disclosed architecture facilitates the sandboxing of applications by taking core operating system components that normally run in the operating system kernel or otherwise outside the...
US20110167183 Minimizing Interconnections In A Multi-Shelf Switching System  
In certain embodiments, minimizing interconnections in a multi-shelf switching system includes receiving a map describing the switching system, where the switching system comprises shelves and...
US20110030030 UNIVERSAL SERIAL BUS - HARDWARE FIREWALL (USB-HF) ADAPTOR  
A system and method in accordance with the present invention provides a protected area for software to execute on a separate hardware firewall adaptor when a storage device is operating in an...
US20110283028 IMPLEMENTING NETWORK MANAGER QUARANTINE MODE  
A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network...
US20140019654 DYNAMIC LINK WIDTH ADJUSTMENT  
Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always...
US20110106987 METHOD FOR CONTROLLING A PLURALITY OF PERSONAL COMPUTER HOSTS BY UTILIZING ONLY ONE PERSONAL COMPUTER HOST, AND ASSOCIATED CONTROLLER AND PERSONAL COMPUTER  
A controller includes a first USB interface, a second USB interface and a control circuit, where the first USB interface is utilized for connecting to a first personal computer host, and the...
US20090013113 Methods and systems for interprocessor message exchange between devices using only write bus transactions  
Systems and methods for reducing or eliminating use of read transactions by a message consuming device coupled through a shared bus to a message producing device to transfer a message from the...
US20080148036 Computer Compliance Enforcement  
A security module for a pay-per-use computer supplies an appropriate BIOS for a given mode of operation. A power manager in the security module powers only essential circuits until the BIOS is...
US20120203944 Systems and Methods for Providing Access to Financial Trading Services  
A system and method to allow service consumers to access financial services deployed using various integration technologies with optimal latency through a technique of data-driven bus arbitration...
US20100332707 Bi-directional handshake for advanced reliabilty availability and serviceability  
In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from...
US20100082862 UNIVERSAL SERIAL BUS ENDPOINT CONTEXT CACHING  
According to some embodiments, an apparatus may be capable of exchanging information with t potential universal serial bus endpoints, where t is an integer greater than 1. Moreover, x endpoint...
US20120151104 PIO INTERJECTION BETWEEN BEATS OF A DMA OPERATION  
Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may...
US20050138251 Arbitration of asynchronous and isochronous requests  
Machine-readable media, methods, and apparatus are described to arbitrate between asynchronous requests and isochronous requests. In one embodiment, an arbiter defines a service period comprising...
US20080282006 Latency Hiding for a Memory Management Unit Page Table Lookup  
In certain systems, local request's require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency...
US20080301343 DEVICE FOR CONTROLLING COMMUNICATION BETWEEN A MODULE AND A TRANSMISSION BUS  
The invention relates to a device for controlling communication between a module (10) and a transmission bus (22), comprising a communication control unit (23) disposed between the transmission...
US20110238904 ALIGNMENT OF INSTRUCTIONS AND REPLIES ACROSS MULTIPLE DEVICES IN A CASCADED SYSTEM, USING BUFFERS OF PROGRAMMABLE DEPTHS  
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or...
US20080209094 Bus-based communication system  
A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the component...
US20150178231 DETERMINING COMMAND RATE BASED ON DROPPED COMMANDS  
In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes;...
US20150178230 DETERMINING COMMAND RATE BASED ON DROPPED COMMANDS  
In one or more embodiments, one or more systems, devices, methods, and/or processes described can send, via an interconnect, a rate master command to at least one of multiple processing nodes;...
US20120079148 REORDERING ARRANGEMENT  
An embodiment of a network-on-chip is provided. The network-on-chip includes a plurality of sources of requests and a plurality of destinations for requests. The plurality of destinations are...
US20120221753 METHOD AND DEVICE FOR WAKING UP USERS IN A BUS SYSTEM AND CORRESPONDING USERS  
An apparatus for waking up users of a CAN bus system, a sensing element being provided which senses at least one predefined signal property of the signals transmitted on the bus system and the...
US20150019775 Single Wire Programming and Debugging Interface  
A microcontroller has a housing with external pins and an integrated debugging interface using only a single signal pin. In a method for operating a microcontroller as described above, the method...
US20150006774 SYSTEM AND METHOD FOR CONTROLLING A BUS IN RESPONSE TO AN INDICATION OF BUS CAPACITY IN A PORTABLE COMPUTING DEVICE  
Systems and methods for real-time control of a bus operating point in a portable computing device (“PCD”) are presented. An indication of an event occurring in a bus interface is used as an...
US20140095751 FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE  
Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake...
US20110246692 Implementing Control Using A Single Path In A Multiple Path Interconnect System  
A method and circuit for implementing control using a single path in a multiple path interconnect system, and a design structure on which the subject circuit resides are provided. Control TL...
US20070283068 Circuit and Method for Providing Access to a Test and/or Monitoring System  
A circuit (10) and method for providing test and/or monitoring access to at least two telecommunication lines (18). This circuit (10) comprises at least one bus (12) and at least two primary...
US20080147939 BROADCASTING DATA ON A PERIPHERAL COMPONENT INTERCONNECT BUS  
A method for broadcasting data on a peripheral component interconnect bus includes coupling at least one master agent, at least one responding target agent and at least one snooping target agent...
US20080086580 System and method for managing baseboard management controller  
This invention discloses a system and method for managing baseboard management controller. The system comprising: at least one BMC; at least one primary node board, connecting to said at least one...
US20100262734 WIRELESS USB DEVICE FOR NETWORKING WITH MULTIPLE WIRELESS USB HOSTS AND METHOD THEREOF  
Provided are a Wireless USB device for networking with multiple Wireless USB hosts and a method thereof. The Wireless USB device includes a selection unit for selecting a device management unit...
US20050060453 Instruction supply control unit and semiconductor device  
The instruction supply control unit of this invention for appropriately selecting one master to be given a bus use right from a plurality of masters and supplying instructions issued by the...
US20100023662 BUS MASTERING METHOD  
A mastering method of a bus includes the following steps: receiving a command; determining if the command is a bus master command to generate a determined result; outputting at least one break...
US20130198426 HETEROGENEOUS PARALLEL SYSTEMS FOR ACCELERATING SIMULATIONS BASED ON DISCRETE GRID NUMERICAL METHODS  
A system for executing a given scientific code using a suitable finite-volume or finite-element solver for a large dataset represented as a grid, comprising a plurality of equal computing nodes...
US20070112984 Sideband bus setting system and method thereof  
A sideband bus setting system in which multiple target devices (ICs) are communicably connected to a master device through a bus so as to set data to ICs mounted on an electronic device. The...
US20120210028 SERVICE SCHEDULING SYSTEM AND METHOD, AND CONTROL DEVICE  
The disclosure discloses a service scheduling system, a service scheduling method, and a control device; the control device is added to the service scheduling system, and the control device...
US20100017551 BUS ACCESS MODERATION SYSTEM  
A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to...
US20110119410 SERVER SYSTEM  
A server system is provided. The server system includes a baseboard and a plurality of motherboards. The baseboard includes a baseboard management controller (BMC). The motherboards are connected...
US20110125944 Synchronising activities of various components in a distributed system  
An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and...
US20070005855 SIGNAL GENERATING CIRCUIT AND RELATED METHOD FOR ACTIVATING PHYSICAL CHANNEL BETWEEN HOST AND PERIPHERAL DEVICE  
A signal generating circuit of a peripheral device for sending a frame information structure (FIS) to a host via a serial transmission channel to change a busy bit representing the state of the...
US20090254687 ELECTRONIC DEVICE FOR CONTENTION DETECTION OF BIDIRECTIONAL BUS AND RELATED METHOD  
An electronic device of detecting contention of a bidirectional bus for avoiding failing to drive a bidirectional bus due to bus contention includes: an output terminal, an input terminal and a...
US20080140890 Electronic Circuit Arrangement For Detecting a Failing Clock  
The invention relates to an electronic circuit arrangement (300) comprising a clock fail circuit (302) arranged for receiving a clock signal circuit (303) and generating an error signal upon the...
US20110258352 Inline PCI-IOV Adapter  
A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of...
US20080244129 MASTER DEVICE OF TWO-WIRE BUS PROVIDING RELEASE FUNCTION FOR CLOCK LINE AND METHOD THEREOF  
Disclosed is a master device which is capable of communicating with a salve device via a two-wire bus having a clock line and a data line. The master device includes a data port, a clock port and...
US20080228974 Design Structure for a Livelock Resolution Circuit  
A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request...

Matches 1 - 50 out of 220 1 2 3 4 5 >