Matches 1 - 8 out of 8


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US20120078993 Reduced-Level Two's Complement Arithmetic Unit  
A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement...
US20080177816 Method And Decimal Arithmetic Logic Unit Structure To Generate A Magnitude Result of a Mathematic  
A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in...
US20120066282 Whole 1 number method of integer factorization  
Disclosed is a method for factoring integers by squaring computation time. The present invention uses binary numbers to process invert function of multiplication as factorization. Inverse method...
US20120089658 MODULO OPERATION METHOD AND APPARATUS FOR SAME  
The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the...
US20070266073 Method and apparatus for decimal number addition using hardware for binary number operations  
According to embodiments of the subject matter disclosed in this application, decimal floating-point additions and/or decimal fixed-point additions may be implemented using existing hardware for...
US20140149481 Decimal Multi-Precision Overflow and Tininess Detection  
An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory...
US20110078653 ADDING SIGNED 8/16/32-BIT INTEGERS TO 64-BIT INTEGERS  
Disclosed are methods, apparatus, and computer-readable media for generating output computer code that adds a 64-bit integer to a smaller-length integer having a length of less than 64 bits. Input...
US20160062752 METHOD, PROGRAM, AND SYSTEM FOR CODE OPTIMIZATION  
Method, program and system for code optimization. A sign assignment instruction with identically sized packed decimal format input and output operands is detected where the sign assignment...
Matches 1 - 8 out of 8