Match

Document 
Document Title 

US20130138711 
SHARED INTEGER, FLOATING POINT, POLYNOMIAL, AND VECTOR MULTIPLIER
A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the... 

US20110289131 
MACHINE DIVISION
Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical... 

US20140101220 
COMPOSITE FINITE FIELD MULTIPLIER
A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n)... 

US20140164457 
EXTENSIBLE ITERATIVE MULTIPLIER
An extensible iterative multiplier design is provided. Embodiments provide cascaded 8bit multipliers for simplifying the performance of multibyte multiplications. Booth encoding is performed in... 

US20140067897 
FORMAL VERIFICATION OF BOOTH MULTIPLIERS
Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth... 

US20110246119 
PROCESS FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO A SIDE CHANNEL ANALYSIS
A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a... 

US20150095396 
MULTIPLYING VARYING FIXEDPOINT BINARY NUMBERS
Methods and systems for multiplying varying cast numbers are described herein. By using information related to the inputs to be multiplied, a single multiplier module may be used to multiply many... 

US20050198093 
Montgomery modular multiplier
In a Montgomery multiplier, a modulus product generator may select a modulus product from a plurality of selectable nbit modulus numbers M, a given modulus number M being formed from a currently... 

US20080063189 
OPTIMAL SIGNEDDIGIT RECODING FOR ELLIPTIC CURVE CRYPTOGRAPHY
An apparatus and method is described of reducing joint weight for integers involved in a scalar multiplication, such as during cryptography. By way of example, the method is utilized within... 

US20080077647 
Parameterized VLSI Architecture And Method For Binary Multipliers
Systems and methods of multiplying binary numbers are disclosed. In one such system there is a Sigma unit and an Omega unit. The Sigma unit may generate partial sums of the multiplier and shifted... 

US20090006517 
UNIFIED INTEGER/GALOIS FIELD (2m) MULTIPLIER ARCHITECTURE FOR ELLIPTICCURVE CRYTPOGRAPHY
A unified integer/GaloisField 2m multiplier performs multiply operations for publickey systems such as Rivert, Shamir, Aldeman (RSA), DiffieHellman key exchange (DH) and Elliptic Curve... 

US20080256164 
METHODS AND APPARATUS FOR CARRY GENERATION IN A BINARY LOOK AHEAD SYSTEM
Methods and apparatus provide for a carry generation tree for a carry lookahead binary adder, which includes N stages of operators, reducers, and/or repeaters, wherein: a first of the stages... 

US20100005131 
Powerresidue calculating unit and method of controlling the same
A powerresidue calculating unit according to one embodiment of the present invention includes a multiplication residue calculating unit performing a multiplication calculation and a residue... 

US20050223054 
Multiplier sign extension method and architecture
A multiplier sign extension method and architecture are used for encoding operations of a multiplier of a digital signal processor. The multiplier sign extension method comprises the steps of:... 

US20100191787 
Sequential Multiplier
A sequential multiplier for multiplying a binary multiplier and a binary multiplicand to produce a final product. A first logic circuit generates a control signal based on the multiplier. A second... 

US20060235922 
Quisquater Reduction
A method and apparatus for calculating the product P of a first number X and a second number Y, modulo N, where Y is partitioned into j words each of length p bits, and has a length (m+n) bits,... 

US20070174379 
Presaturating fixedpoint multiplier
A presaturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier... 

US20080222227 
Design Structure for a Booth Decoder
A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second... 

US20100057824 
METHOD AND SYSTEM FOR PROCESSING THE BOOTH ENCODING 33RD TERM
A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central... 

US20130304787 
DIGITAL SERIAL MULTIPLIER
A multiplier of a binary number A by a binary number B may be configured to add each term AiBj with a left shift by i+j bits, where Ai is the bit of weight i of number A, and Bj the bit of weight... 

US20100306293 
Galois Field Multiplier
A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the... 

US20090132630 
METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS
Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating... 

US20090083360 
Shiftadd based parallel multiplication
A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bitpositions. The first memory holds a first... 

US20120254271 
ARITHMETIC OPERATION CIRCUIT AND METHOD OF CONVERTING BINARY NUMBER
An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number;... 

US20060230094 
Digital signal processing circuit having input register blocks
An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE... 

US20140136588 
METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS
Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating... 

US20100325188 
PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR MULTIPLICATION OF LARGE OPERANDS
A processor including instruction support for implementing largeoperand multiplication may issue, for execution, programmerselectable instructions from a defined instruction set architecture... 

US20090136022 
Method and Apparatus for Calculating a Polynomial Multiplication, In Particular for Elliptic Curve Cryptography
Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy... 

US20130144927 
METHOD AND APPARATUS FOR PERFORMING MULTIPLICATION IN A PROCESSOR
A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64bit multiplier and a 64bit multiplicand may be multiplied together... 

US20100153830 
CARRY BUCKETAWARE MULTIPLICATION
An apparatus comprising an integrated circuit configured to accept a plurality of operands; multiply the operands producing an result in a first binary format; and distribute the result in the... 

US20100198895 
Digital Signal Processor Having Instruction Set With A Logarithm Function Using Reduced LookUp Table
A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced lookup table. The disclosed digital signal processor evaluates a logarithm function... 

US20160041946 
PERFORMING A COMPARISON COMPUTATION IN A COMPUTER SYSTEM
A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a... 

US20160034257 
GENERATING A HASH USING SBOX NONLINEARIZING OF A REMAINDER INPUT
A processor includes a hash register and a hash generating circuit. The hash generating circuit includes a novel programmable nonlinearizing function circuit as well as a modulo2 multiplier, a... 

US20150347090 
FLOATING POINT MULTIPLY ACCUMULATOR MULTIPRECISION MANTISSA ALIGNER
A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bitshifting circuit that is communicatively... 

US20150317126 
Approximating Functions
A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients... 