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US20140046996 |
UNIFIED COMPUTATION SYSTEMS AND METHODS FOR ITERATIVE MULTIPLICATION AND DIVISION, EFFICIENT OVERFLOW DETECTION SYSTEMS AND METHODS FOR INTEGER DIVISION, AND TREE-BASED ADDITION SYSTEMS AND METHODS FOR SINGLE-CYCLE MULTIPLICATION
A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a... |
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US20100318592 |
Multiplicative Division Circuit With Reduced Area
The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The... |
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US20140067896 |
Universe has an End
The “Big Bung!” was not at the beginning of Universe! |
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US20110289131 |
MACHINE DIVISION
Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical... |
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US20140280406 |
SYSTEMS AND METHODS FOR ESTIMATING UNCERTAINTY
A computer-implemented method includes receiving instructions to execute an analytic, wherein the instructions comprise one or more analytic inputs and a corresponding one or more uncertainty... |
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US20140101220 |
COMPOSITE FINITE FIELD MULTIPLIER
A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n)... |
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US20120226731 |
LOW DEPTH COMBINATIONAL FINITE FIELD MULTIPLIER
A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of... |
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US20080225939 |
MULTIFUNCTIONAL VIDEO ENCODING CIRCUIT SYSTEM
The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation,... |
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US20140046991 |
ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM
An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive... |
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US20120221618 |
ENCRYPTION METHOD COMPRISING AN EXPONENTIATION OPERATION
A method and a device protected against hidden channel attacks includes a calculation of the result of the exponentiation of a data m by an exponent d. The method and the device are configured to... |
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US20130144925 |
SYSTEMS AND METHODS FOR SOLVING COMPUTATIONAL PROBLEMS
Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and... |
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US20070192399 |
Power-efficient sign extension for booth multiplication methods and systems
Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. Power-efficient sign extension for Booth multiplication... |
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US20120203814 |
COMPUTER FOR AMDAHL-COMPLIANT ALGORITHMS LIKE MATRIX INVERSION
A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the... |
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US20130080491 |
FAST CONDITION CODE GENERATION FOR ARITHMETIC LOGIC UNIT
In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the... |
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US20110231468 |
HIGH-RADIX MULTIPLIER-DIVIDER
The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence... |
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US20100306292 |
DSP Engine with Implicit Mixed Sign Operands
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit... |
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US20120197956 |
CALCULATING UNIT FOR REDUCING AN INPUT NUMBER WITH RESPECT TO A MODULUS
A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions... |
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US20050120069 |
Dynamically reconfigurable power-aware, highly scaleable multiplier with reusable and locally optimized structures
A large bit width multiplier with multiple copies of a core small bit width multiplier and ROM cells. The present invention provides a power system that trades off processing speed against power... |
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US20150199303 |
Device and Method for Determining an Estimate of the Logarithm of an Input Variable
The disclosure relates to a device for determining an estimate of the logarithm of an input variable. The device has an approximation unit which is designed to use an approximation to determine... |
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US20140095572 |
Multiply and Accumulate Feedback
A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus (260) comprising a multiplier stage (264) having an output coupled to an... |
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US20070192398 |
Booth multiplier with enhanced reduction tree circuitry
Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. A modified Booth multiplication system and process... |
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US20070299899 |
Mulptiplying two numbers
Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba... |
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US20050182813 |
Apparatus and method of multiplication using a plurality of identical partial multiplication modules
A multiplication apparatus including a multiplier and multiplicand extractor for dividing the multiplicand into partial multiplicands and dividing the multiplier into partial multipliers, and for... |
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US20080275932 |
Integer Division In A Manner That Counters A Power Analysis Attack
In the course of performing an Elliptic Curve Scalar Multiplication operation by Additive Splitting Using Division, a main loop of an integer division operation may be performed. The integer... |
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US20090006509 |
High-radix multiplier-divider
The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence... |
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US20070100924 |
Asynchronous signed multiplier and algorithm thereof
An asynchronous signed multiplier including N pieces of partial product generators (PPGs), an operation module and a leading-zero-bit-detector is provided. The partial product generator generates... |
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US20090157790 |
METHOD AND APPARATUS FOR MULTIPLYING POLYNOMIALS WITH A PRIME NUMBER OF TERMS
An efficient method and apparatus to compute a product of polynomials of degree n−1 where n is an arbitrary prime is provided. The total number of multiply operations and Arithmetic Logical Unit... |
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US20090138744 |
MULTIPLIER DEVICE WITH SUPPRESSION OF HIGHER-ORDER DISTORTION
A multiplier device is configured to include first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical,... |
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US20050138102 |
Arithmetic unit
An arithmetic unit is provided which is capable of enhancing area efficiency while suppressing operating speed reduction. A third partial product adder (T101) is divided into a high order part... |
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US20060184603 |
Zero detect in partial sums while adding
The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting... |
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US20120144161 |
CARRYLESS MULTIPLICATION PREFORMATTING APPARATUS AND METHOD
An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless... |
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US20060143260 |
Low-power booth array multiplier with bypass circuits
A low-power Booth array multiplier with bypass circuits is provided. The multiplier includes a first encoder for Booth-encoding the multiplier; a second encoder for pre-encoding the multiplier to... |
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US20140258352 |
SPACE DILATING TWO-WAY VARIABLE SELECTION
A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue... |
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US20060242219 |
Asynchronous multiplier
An asynchronous multiplier is provided. The multiplier comprises a partial product generator, an addition array, a leading-zero-bit detector, a final-stage adder and a completion detector. The... |
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US20130031154 |
SELF-TIMED MULTIPLIER
A self-timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of... |
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US20080104163 |
Non-Uniform Sampling To Avoid Aliasing
A method for sampling includes selecting and sampling at uniform time steps over a collection time that is more than one period. Reordering the collected samples into “one period” and transforming... |
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US20130144926 |
MINIMUM MEAN SQUARE ERROR PROCESSING
A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the... |
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US20100063986 |
COMPUTING DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT
In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a... |
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US20060253521 |
High-Speed Integer Multiplier Unit Handling Signed and Unsigned Operands and Occupying a Small Area
A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which indicates whether the corresponding... |
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US20100023569 |
METHOD FOR COMPUTERIZED ARITHMETIC OPERATIONS
A method of computing arithmetic operations more efficiently than the conventional Arithmetic Logic Unit (ALU) is disclosed. By encoding both operands from Binary Coded Decimal (BCD) codes (0000,... |
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US20070255780 |
Method and system for creating a multiplication and division puzzle
A multiplication and division puzzle and method of making thereof include a main table having a plurality of cells in rows and columns, the cells being filled with products and multipliers. A... |
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US20080208940 |
RECONFIGURABLE CIRCUIT
A reconfigurable circuit including a multiplier for multiplying a value, an accumulator for cumulatively adding said multiplied value and a round-off processing unit for rounding off said... |
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US20150058389 |
EXTENDED MULTIPLY
Techniques are disclosed relating to performing extended multiplies without a carry flag. In one embodiment, an apparatus includes a multiply unit configured to perform multiplications of operands... |
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US20060020655 |
Library of low-cost low-power and high-performance multipliers
Disclosed is an apparatus and method for producing a library of low-cost, low-power multipliers which are easy to build, have self testing capabilities, and are regular. The multipliers multiply a... |
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US20080065714 |
DEVICE AND METHOD FOR CALCULATING A RESULT OF A MODULAR MULTIPLICATION WITH A CALCULATING UNIT SMALLER THAN THE OPERANDS
For calculating a result of a modular multiplication with long operands, at least the multiplicand is divided into at least three shorter portions. Using the three shorter portions of the... |
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US20060195503 |
Integrated circuit including at least one configurable logic cell capable of multiplication
The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial... |
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US20100011047 |
Hardware-Based Cryptographic Accelerator
A system, method, and apparatus for performing hardware-based cryptographic operations are disclosed. The apparatus can include an encryption device with a hardware accelerator having an... |
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US20100306298 |
DEVICE FOR DFT CALCULATION
A device to perform DFT calculations, for example in a GNSS receiver, including two banks of multipliers by constant integer value, the values representing real and imaginary part of twiddle... |
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US20080065900 |
METHOD AND APPARATUS FOR BIOMETRICS
An apparatus and method for biometrics are provided. The apparatus includes a user registration unit, a user authentication unit, and a transform key storing unit. The user registration unit store... |
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US20060041610 |
Processor having parallel vector multiply and reduce operations with sequential semantics
A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit... |