Match

Document 
Document Title 

US20140280426 
INFORMATION RETRIEVAL USING SPARSE MATRIX SKETCHING
Embodiments of the invention include method of approximating a matrix of data using sparse matrices which includes receiving a first matrix and generating a second matrix based on the first matrix... 

US20100023575 
PREDICTOR
A Predictor is described which is based on a modified RLS (recursive least squares) algorithm. The modifications prevent divergence and accuracy problems when fixed point implementation is used. 

US20130262550 
MATRIX CALCULATION DEVICE, MATRIX CALCULATION METHOD, AND STORAGE MEDIUM HAVING MATRIX CALCULATION PROGRAM STORED THEREON
A matrix calculation device includes a first partition position display unit configured to distinguishably display a partition position of the one matrix partitioned by the matrix partitioning... 

US20140181171 
METHOD AND SYSTEM FOR FAST TENSORVECTOR MULTIPLICATION
A method and a system for fast tensorvector multiplication provide factoring an original tensor into a kernel and a commutator, multiplying the kernel obtained by the factoring of the original... 

US20140289301 
MATRIX CALCULATION APPARATUS, MATRIX CALCULATION METHOD, AND COMPUTER READABLE MEDIUM HAVING MATRIX CALCULATION PROCESS PROGRAM STORED THEREON
There is provided a matrix calculation apparatus. The apparatus includes: a matrix calculation formula display controller configured to display a matrix calculation formula on a display unit,... 

US20150199301 
METHOD AND DEVICE FOR OBTAINING THREEPHASE POWER FLOW OF POWER DISTRIBUTION NETWORK WITH UNGROUNDED TRANSFORMERS
A method for obtaining a threephase power flow of a power distribution network and a device for obtaining a threephase power flow of a power distribution network are provided. The method... 

US20140108481 
UNIVERSAL FPGA/ASIC MATRIXVECTOR MULTIPLICATION ARCHITECTURE
A universal singlebitstream FPGA library or ASIC implementation accelerates matrixvector multiplication processing multiple matrix encodings including dense and multiple sparse formats. A... 

US20070271325 
Matrix multiply with reduced bandwidth requirements
Systems and methods for reducing the bandwidth needed to read the inputs to a matrix multiply operation may improve system performance. Rather than reading a row of a first input matrix and a... 

US20060155798 
Eigenvalue decomposition and singular value decomposition of matrices using jacobi rotation
Techniques for decomposing matrices using Jacobi rotation are described. Multiple iterations of Jacobi rotation are performed on a first matrix of complex values with multiple Jacobi rotation... 

US20120317160 
MATRIX CALCULATION METHOD, PROGRAM, AND SYSTEM
A matrix calculation system for calculating funny matrix multiplication (FMM) of a matrix A and a matrix B, including: sequentially calculating a permutation of indices {ai} in which values are... 

US20100011040 
Device and method for solving a system of equations characterized by a coefficient matrix comprising a Toeplitz structure
A device comprising digital circuits for calculating an unknown solution vector X in a system of equations with a known coefficient matrix T and a known vector Y, has a first vector transformer... 

US20120203815 
MATRIX CALCULATION METHOD, PROGRAM, AND SYSTEM
A matrix calculation method and system for calculating funny matrix multiplication (FMM) of a matrix A and a matrix B, including: sequentially calculating a permutation of indices {ai} in which... 

US20060259535 
Tonal rotors
A set of complex rotations are used to implement a unitary “Q” matrix that can arise in various transmitters and/or receivers in communication line vectoring. Each complex rotation is a set of... 

US20100306299 
Circuits and Methods for Performing Exponentiation and Inversion of Finite Field Elements
An exponentiation circuit for computing an exponential power of a finite field element includes combinatory logic circuits that map input digits of a multidigit field element P to output digits... 

US20090172052 
TILED ARCHITECTURE FOR STATIONARYMETHOD ITERATIVE LINEAR SOLVERS
A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate... 

US20050240646 
Reconfigurable matrix multiplier architecture and extended borrow parallel counter and smallmultiplier circuits
A dynamically or runtime reconfigurable matrix multiplier architecture with a reconfiguration mechanism for computing the product of matrices Xp×r and Yr×q for any integers p, q, r and any item... 

US20110078226 
Sparse MatrixVector Multiplication on Graphics Processor Units
Techniques for optimizing sparse matrixvector multiplication (SpMV) on a graphics processing unit (GPU) are provided. The techniques include receiving a sparse matrixvector multiplication,... 

US20090292520 
SOLVER FOR HARDWARE BASED COMPUTING
FullAC load flow constitutes a core computation in power system analysis. The present invention provides a performance gain with a hardware implementation of a sparselinear solver using a Field... 

US20090043836 
METHOD AND SYSTEM FOR LARGE NUMBER MULTIPLICATION
Methods, apparatus and systems for large number multiplication. A multiplication circuit is provided to compute the product of two operands (A and B), at least one of which is wider than a width... 

US20090292758 
Optimized Corner Turns for Local Storage and Bandwidth Reduction
A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing... 

US20060106910 
Galois field polynomial multiplication
In one aspect, a multiplier for performing multiplication of a first operand and a second operand is provided. The multiplier comprises a matrix having a plurality of matrix elements arranged in a... 

US20080126468 
Decoding apparatus for vector booth multiplication
A decoding apparatus for Booth multiplication includes a NAND gate, a first and a second OR gate coupled to the NAND gate, a first and a second exclusive NOR gate coupled respectively to the OR... 

US20090030964 
MATRIX OPERATION DEVICE
There is provided a matrix operation device comprising a k201th power weighting multiplication circuit (202) for weighting inputs with k201th power weighting coefficients (202b) which are... 

US20150074163 
PRODUCTSUM OPERATION CIRCUIT AND PRODUCTSUM OPERATION SYSTEM
A productsum operation circuit that performs a matrix product of a firstmatrix and a secondmatrix to output a thirdmatrix, includes; a plurality of multipliers; a plurality of firstadders... 

US20110125819 
MINIMUM MEAN SQUARE ERROR PROCESSING
A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the... 

US20090300091 
Reducing Bandwidth Requirements for Matrix Multiplication
A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing... 

US20090154579 
QR DECOMPOSITION APPARATUS AND METHOD FOR MIMO SYSTEM
Provided is a QR decomposition apparatus and method that can reduce the number of computers by sharing hardware in an MIMO system employing OFDM technology to simplify a structure of hardware. The... 

US20090006508 
Method and apparatus for extrapolating diagnostic data
A method and an apparatus for extrapolating diagnostic data relating to one pupil diameter to another pupil diameter. Embodiments according to the invention are more particularly directed to... 

US20120136912 
APPARATUS AND METHOD FOR GENERATING CODEBOOK IN WIRELESS COMMUNICATION SYSTEM
An apparatus and method for generating a codebook in a wireless communication system are disclosed. The codebook generation method includes determining one or more dominant singular vectors in a... 

US20090024685 
High Speed and Efficient Matrix Multiplication Hardware Module
A matrix multiplication module and matrix multiplication method are provided that use a variable number of multiplieraccumulator units based on the amount of data elements of the matrices are... 

US20060173948 
Scalable 2X2 rotation processor for singular value decomposition
A twoplane rotation (TPR) approach to Gaussian elimination (Jacobi) is used for computational efficiency in determining rotation parameters. A rotation processor is constructed using the TPR... 

US20150088954 
System and Method for Sparse Matrix Vector Multiplication Processing
Systems and methods for sparse matrix vector multiplication (SpMV) are disclosed. The systems and methods include a novel streaming reduction architecture for floating point accumulation and a... 

US20120278376 
SYSTEM AND METHOD FOR SPARSE MATRIX VECTOR MULTIPLICATION PROCESSING
Systems and methods for sparse matrix vector multiplication (SpMV) are disclosed. The systems and methods include a novel streaming reduction architecture for floating point accumulation and a... 

US20120203816 
Optimized Corner Turns for Local Storage and Bandwidth Reduction
A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing... 

US20110153702 
MULTIPLICATION OF A VECTOR BY A PRODUCT OF ELEMENTARY MATRICES
A method, system and computer program product to improve multiplication of a vector by a product of elementary matrices. The method includes, for example, receiving an input vector and... 

US20060173947 
Method and structure for a hybrid fullpacked storage format as a single rectangular format data structure
A method (and structure) of linear algebra processing, includes processing a (real or complex) matrix data having elements originally stored in one of a triangular format and a symmetric matrix... 

US20140280428 
INFORMATION RETRIEVAL USING SPARSE MATRIX SKETCHING
A system for retrieving stored data includes memory and a processor. The memory stores a first matrix, A, having dimensions n×d, a first sparse matrix, R, and a second sparse matrix, S. The... 

US20100011041 
Device and method for determining signals
Many signal processing devices require the solution to a system of equations with a Toeplitz, or block Toeplitz, coefficient matrix. This solution can be obtained with increased efficiency by... 

US20110040821 
Matrix Multiplication Operations with Data PreConditioning in a High Performance Computing Architecture
Mechanisms for performing matrix multiplication operations with data preconditioning in a high performance computing architecture are provided. A vector load operation is performed to load a... 

US20140032625 
Floating point matrix multiplication coprocessor
Invention providing a means for performing matrix multiplication that may be implemented in hardware or software. The invention is scalable to matrices of varying dimension and to permit balancing... 

US20100011044 
Device and method for determining and applying signal weights
The solution X0 to an initial system of equations with a Toeplitz coefficient matrix T0 can be efficiently determined from an approximate solution X to a system of equations with a coefficient... 

US20050125477 
Highprecision matrixvector multiplication on a chargemode array with embedded dynamic memory and stochastic method thereof
Analog computational arrays for matrixvector multiplication offer very large integration density and throughput as, for instance, needed for realtime signal processing in video. Despite the... 

US20070297614 
Device, System and Method for Fast Secure Message Encryption Without Key Distribution
One party sends a securely encrypted message to a second party. Each party chooses a secret message key for the message, which is never shared with or transmitted to any other party. The message... 

US20140046995 
PARALLEL IMPLEMENTATION OF MAXIMUM A POSTERIORI PROBABILITY DECODER
A MAP decoder may be implemented in parallel. In one implementation, a device may receive an input array that represents received encoded data and calculate, in parallel, a series of transition... 

US20100325187 
EFFICIENT MATRIX MULTIPLICATION ON A PARALLEL PROCESSING DEVICE
The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix... 

US20080279274 
CIRCUIT AND METHOD FOR GENERATING FIXED POINT VECTOR DOT PRODUCT AND MATRIX VECTOR VALUES
An integrated circuit (102) and method computes fixed point vector dot products (424) and/or matrix vector products using a type of distributed architecture that loads bit planes (add00add30) and... 

US20100153477 
METHOD OF CALCULATING TRANSPORT BLOCK SIZES IN COMMUNICATION SYSTEM
A method of calculating a transport block size in an HSPA receiver of a communication system is provided. After decomposing an exponential function Pk into a plurality of constant vectors, the... 

US20100042666 
METHOD AND DEVICE FOR DETECTING TRANSMISSION SIGNAL WITH DIVISION DETECTION
The present invention relates to a method and device for detecting a transmission signal on the basis of a received signal by applying a division and detection algorithm. An embodiment of the... 

US20110040822 
Complex Matrix Multiplication Operations with Data PreConditioning in a High Performance Computing Architecture
Mechanisms for performing a complex matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the complex matrix multiplication operation... 

US20100250635 
VECTOR MULTIPLICATION PROCESSING DEVICE, AND METHOD AND PROGRAM THEREOF
Intended is to reduce power consumption without requiring shift of an operand. A vector multiplication processing device comprising a speedup circuit (a fixed point overflow foresight circuit 5... 