Matches 1 - 16 out of 16


Match Document Document Title
US20120311008 SMART ROUNDING SUPPORTING PSYCHOLOGICAL PRICING  
Pricing values may be automatically computed by converting a base price with a predefined price ending based on predetermined rounding rules. A base price may be adjusted employing a rounding...
US20120215825 EFFICIENT MULTIPLICATION TECHNIQUES  
Techniques are disclosed that involve the multiplication of values. For instance, a plurality of partial products may be calculated from a first operand and a second operand. This calculating...
US20110185000 Method for carry estimation of reduced-width multipliers  
A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies...
US20110320512 Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection  
A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes...
US20100306292 DSP Engine with Implicit Mixed Sign Operands  
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit...
US20130007085 Method and Apparatus For Performing Lossy Integer Multiplier Synthesis  
A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the...
US20060230093 Digital signal processing circuit having a pattern detector circuit for convergent rounding  
An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input...
US20080034027 Method for reducing round-off error in fixed-point arithmetic  
Round-off error in fixed-point arithmetic is minimized by changing the magnitudes of two multipliers simultaneously. The dynamic range of an intermediate output is thus maximized to increase...
US20100125620 ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF  
A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first...
US20140181170 ARITHMETIC CIRCUIT AND ARITHMETIC METHOD  
According to one embodiment, an arithmetic circuit includes follows. The arithmetic unit performs an arithmetic operation including addition and multiplication to generate a first value of (n+m)...
US20110225224 Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture  
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with...
US20110270901 Method and System for Bit Stacked Fast Fourier Transform  
An FFT algorithm that splits a large bit width waveform into two parts, making it possible to conduct the FFT with much lower logic resource consumption is disclosed. The waveform is split into...
US20100260429 SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, AND PROGRAM  
A signal processing apparatus according to an embodiment of the present invention includes: a compression processing unit that performs compression processing on n-bit data; a bit-number...
US20100131580 APPARATUS AND METHODS FOR HARDWARE-EFFICIENT UNBIASED ROUNDING  
A system and method for unbiased rounding away from, or toward, zero comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M−N bit number, and...
US20150379526 TRACKING AND LINKING MOBILE DEVICE ACTIVITY  
Methods for tracking mobile devices with increased accuracy include generating a first time-dependent identifier. Generating the first time-dependent identifier includes device information,...
US20150039665 DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION  
A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value...

Matches 1 - 16 out of 16