Matches 1 - 20 out of 20


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US20120221618 ENCRYPTION METHOD COMPRISING AN EXPONENTIATION OPERATION  
A method and a device protected against hidden channel attacks includes a calculation of the result of the exponentiation of a data m by an exponent d. The method and the device are configured to...
US20070162530 Modular reduction for a cryptographic process and corprocessor for carrying out said reduction  
The invention relates to a cryptographic method wherein, in order to carry out a fully polynomial division of type Q(x)[U(x)/N(x)], wherein Q(x), N(x) and U(x) are polynomials, respectively a...
US20090271464 ARITHMETIC OR LOGICAL OPERATION TREE COMPUTATION  
A method of computing at least a first and a second tree of arithmetic or logical operations on a microprocessor comprising at least n parallel processing elements. The method comprises: a)...
US20080046496 Multi-functional keyboard on touch screen  
A touch screen has a keyboard which has several areas of keys. Each area is sizable, including enlarging and shrinking, and movable. Because the sizes of the keys areas are controllable, the...
US20090292757 Method and apparatus for zero prediction  
A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor 115 in use is connected by a controller 110 to an arithmetic unit 120. Different...
US20060277243 Alternate representation of integers for efficient implementation of addition of a sequence of multiprecision integers  
A technique for summing a series of integers of the form ii+i2+i3+ . . . in includes calculating the vector sum of the integers and a vector carry indicative of overflows resulting from generation...
US20060064451 Arithmetic circuit  
A system is described for processing data through single instruction multiple data (SIMD) operations. The system is coupled to receive a first operand and second operand, each of the operands...
US20060288069 Digital signal processing circuit having a SIMD circuit  
An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic...
US20130191431 EFFICIENT FIR FILTERS  
A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes...
US20080147770 INPUT DEVICE  
An input device includes a power unit, a power switch unit, a processing unit, and an input unit. The power switch unit includes a first switch for supplying power to the processing unit when...
US20060288070 Digital signal processing circuit having a pattern circuit for determining termination conditions  
A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output...
US20090265409 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA  
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored...
US20110103578 SYSTEMS AND METHODS FOR EFFICIENTLY CREATING DIGESTS OF DIGITAL DATA  
Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages...
US20100121899 Methods and apparatus for efficient complex long multiplication and covariance matrix implementation  
Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along...
US20090024684 Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units  
A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control...
US20090049113 Method and Apparatus for Implementing a Multiple Operand Vector Floating Point Summation to Scalar Function  
Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises computing an arithmetic result of a...
US20140095571 Processing with Compact Arithmetic Processing Element  
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not...
US20130031153 Processing with Compact Arithmetic Processing Element  
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not...
US20100325186 Processing with Compact Arithmetic Processing Element  
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not...
US20120331028 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA  
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored...

Matches 1 - 20 out of 20