Matches 1 - 36 out of 36


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US20120011181 DECIMAL FLOATING-POINT FUSED MULTIPLY-ADD UNIT  
A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication...
US20120011185 ROUNDING UNIT FOR DECIMAL FLOATING-POINT DIVISION  
A method for performing a decimal floating-point division, including: receiving, by a decimal floating-point divider, a decimal floating-point dividend and a decimal floating-point divisor;...
US20110208794 COMPUTING HALF INSTRUCTIONS OF FLOATING POINT NUMBERS WITHOUT EARLY ADJUSTMENT OF THE SOURCE OPERANDS  
Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and...
US20110302229 CALCULATING LARGE PRECISION COMMON LOGARITHMS  
Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the...
US20120041997 FUSED MULTIPLY-ADD ROUNDING AND UNFUSED MULTIPLY-ADD ROUNDING IN A SINGLE MULTIPLY-ADD MODULE  
A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding...
US20140181169 METHOD, APPARATUS, SYSTEM FOR SINGLE-PATH FLOATING-POINT ROUNDING FLOW THAT SUPPORTS GENERATION OF NORMALS/DENORMALS AND ASSOCIATED STATUS FLAGS  
A mechanism for performing single-path floating-point rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to...
US20130226981 Round for Reround Mode in a Decimal Floating Point Instruction  
A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the...
US20090094308 RELAXED REMAINDER CONSTRAINTS WITH COMPARISON ROUNDING  
A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as...
US20080028014 N-BIT 2's COMPLEMENT SYMMETRIC ROUNDING METHOD AND LOGIC FOR IMPLEMENTING THE SAME  
A rounding circuit is provided that includes an input for receiving a 2's complement number to be rounded. The 2's complement number has a format SXY, where S represents a sign bit, X represents...
US20140101216 MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS  
A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an...
US20130212139 MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS  
A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an...
US20110072066 Apparatus and method for performing fused multiply add floating point operation  
A fused multiply add floating point unit 1 includes multiplying circuitry 4 and adding circuitry 8. The multiply circuitry 4 multiplies operands B and C having N-bit significands to generate an...
US20080215660 Three-Term Input Floating-Point Adder-Subtractor  
The three-term input floating-point adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an...
US20080215659 Round for Reround Mode in a Decimal Floating Point Instruction  
a round-far-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the...
US20090172066 Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away  
Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or...
US20130191433 PERFORMING ROUNDING OPERATIONS RESPONSIVE TO AN INSTRUCTION  
In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the...
US20130304786 DEVICE AND METHOD FOR COMPUTING A FUNCTION VALUE OF A FUNCTION  
A device is provided for computing a function value of a function F. The device includes a memory, a truncator unit, a selector unit, and an evaluator unit. The memory contains a look-up table...
US20070162535 Rounding floating point division results  
A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result...
US20110055307 METHOD FOR FLOATING POINT ROUND TO INTEGER OPERATION  
An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and...
US20130304785 APPARATUS AND METHOD FOR PERFORMING A CONVERT-TO-INTEGER OPERATION  
A data processing apparatus includes processing circuitry for performing a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value. The...
US20100281087 APPROXIMATE SRT DIVISION METHOD  
The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in...
US20130191426 Merged Floating Point Operation Using a Modebit  
A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to...
US20120191767 Circuit which Performs Split Precision, Signed/Unsigned, Fixed and Floating Point, Real and Complex Multiplication  
An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point...
US20120259903 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT  
An arithmetic circuit for rounding pre-rounded data includes a first register to store first-format pre-rounded data that includes a mantissa of a fixed-precision floating-point number using a...
US20090259708 APPARATUS AND METHOD FOR OPTIMIZING THE PERFORMANCE OF X87 FLOATING POINT ADDITION INSTRUCTIONS IN A MICROPROCESSOR  
A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and...
US20110040815 Apparatus and method for performing fused multiply add floating point operation  
A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus 100 has multiplying circuitry 110 configured to multiply operands B and C to generate a product B*C...
US20130282777 System and Method for a Floating-Point Format for Digital Signal Processors  
An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and...
US20170139673 REDUNDANT REPRESENTATION OF NUMERIC VALUE USING OVERLAP BITS  
A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits...
US20170109134 SYSTEM AND METHOD FOR ROUNDING RECIPROCAL SQUARE ROOT RESULTS OF INPUT FLOATING POINT NUMBERS  
Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a...
US20170046128 PROCESSING FIXED AND VARIABLE LENGTH NUMBERS  
Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and...
US20170031655 Rounding Floating Point Numbers  
Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and...
US20170010863 APPARATUS AND METHOD FOR CONTROLLING ROUNDING WHEN PERFORMING A FLOATING POINT OPERATION  
An apparatus and method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation,...
US20160092167 ROUNDING FLOATING POINT NUMBERS  
Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and...
US20160070538 Round For Reround Mode In A Decimal Floating Point Instruction  
A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the...
US20160070536 FLOATING-POINT ARITHMETIC DEVICE, SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM  
A floating-point arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a...
US20160011855 CHECK PROCEDURE FOR FLOATING POINT OPERATIONS  
Method and computer system for implementing an operation on ≧1 floating point input, in accordance with a rounding mode, e.g. using a Newton-Raphson technique. The floating point result comprises...

Matches 1 - 36 out of 36