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Document Title 

US20120011181 
DECIMAL FLOATINGPOINT FUSED MULTIPLYADD UNIT
A decimal floatingpoint FusedMultiplyAdd (FMA) unit that performs the operation of ±(A×B)±C on decimal floatingpoint operands. The decimal floatingpoint FMA unit executes the multiplication... 

US20120011185 
ROUNDING UNIT FOR DECIMAL FLOATINGPOINT DIVISION
A method for performing a decimal floatingpoint division, including: receiving, by a decimal floatingpoint divider, a decimal floatingpoint dividend and a decimal floatingpoint divisor;... 

US20110208794 
COMPUTING HALF INSTRUCTIONS OF FLOATING POINT NUMBERS WITHOUT EARLY ADJUSTMENT OF THE SOURCE OPERANDS
Apparatus and methods are disclosed for a floating point adder having halfadder capability that does not have the overhead of determining halfadder conditions prior to starting the SED, LED, and... 

US20110302229 
CALCULATING LARGE PRECISION COMMON LOGARITHMS
Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the... 

US20120041997 
FUSED MULTIPLYADD ROUNDING AND UNFUSED MULTIPLYADD ROUNDING IN A SINGLE MULTIPLYADD MODULE
A computer processor including a single fusedunfused floating point multiplyadd (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiplyadd rounding... 

US20140181169 
METHOD, APPARATUS, SYSTEM FOR SINGLEPATH FLOATINGPOINT ROUNDING FLOW THAT SUPPORTS GENERATION OF NORMALS/DENORMALS AND ASSOCIATED STATUS FLAGS
A mechanism for performing singlepath floatingpoint rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to... 

US20130226981 
Round for Reround Mode in a Decimal Floating Point Instruction
A roundforreround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the... 

US20090094308 
RELAXED REMAINDER CONSTRAINTS WITH COMPARISON ROUNDING
A system and method for efficient floatingpoint rounding in computer systems. A computer system may include at least one floatingpoint unit for floatingpoint arithmetic operations such as... 

US20080028014 
NBIT 2's COMPLEMENT SYMMETRIC ROUNDING METHOD AND LOGIC FOR IMPLEMENTING THE SAME
A rounding circuit is provided that includes an input for receiving a 2's complement number to be rounded. The 2's complement number has a format SXY, where S represents a sign bit, X represents... 

US20140101216 
MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS
A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an... 

US20130212139 
MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS
A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an... 

US20110072066 
Apparatus and method for performing fused multiply add floating point operation
A fused multiply add floating point unit 1 includes multiplying circuitry 4 and adding circuitry 8. The multiply circuitry 4 multiplies operands B and C having Nbit significands to generate an... 

US20080215660 
ThreeTerm Input FloatingPoint AdderSubtractor
The threeterm input floatingpoint addersubtractor includes a preprocessing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an... 

US20080215659 
Round for Reround Mode in a Decimal Floating Point Instruction
a roundfarreround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the... 

US20090172066 
Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away
Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or... 

US20130191433 
PERFORMING ROUNDING OPERATIONS RESPONSIVE TO AN INSTRUCTION
In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the... 

US20130304786 
DEVICE AND METHOD FOR COMPUTING A FUNCTION VALUE OF A FUNCTION
A device is provided for computing a function value of a function F. The device includes a memory, a truncator unit, a selector unit, and an evaluator unit. The memory contains a lookup table... 

US20070162535 
Rounding floating point division results
A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result... 

US20110055307 
METHOD FOR FLOATING POINT ROUND TO INTEGER OPERATION
An apparatus and method for computing a rounded floating point number. A floating point unit (FPU) receives an instruction to round a floating point number to a nearest integral value and... 

US20130304785 
APPARATUS AND METHOD FOR PERFORMING A CONVERTTOINTEGER OPERATION
A data processing apparatus includes processing circuitry for performing a converttointeger operation for converting a floatingpoint value to a rounded two's complement integer value. The... 

US20100281087 
APPROXIMATE SRT DIVISION METHOD
The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductorbased computational device situated in... 

US20130191426 
Merged Floating Point Operation Using a Modebit
A first floatingpoint operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to... 

US20120191767 
Circuit which Performs Split Precision, Signed/Unsigned, Fixed and Floating Point, Real and Complex Multiplication
An integrated multiplier circuit that operates on a variety of data formats including integer fixed point, signed or unsigned, real or complex, 8 bit, 16 bit or 32 bit as well as floating point... 

US20120259903 
ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT
An arithmetic circuit for rounding prerounded data includes a first register to store firstformat prerounded data that includes a mantissa of a fixedprecision floatingpoint number using a... 

US20090259708 
APPARATUS AND METHOD FOR OPTIMIZING THE PERFORMANCE OF X87 FLOATING POINT ADDITION INSTRUCTIONS IN A MICROPROCESSOR
A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and... 

US20110040815 
Apparatus and method for performing fused multiply add floating point operation
A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus 100 has multiplying circuitry 110 configured to multiply operands B and C to generate a product B*C... 

US20130282777 
System and Method for a FloatingPoint Format for Digital Signal Processors
An embodiment of a system and method for performing a numerical operation on input data in a hybrid floatingpoint format includes representing input data as a sign bit, exponent bits, and... 

US20170139673 
REDUNDANT REPRESENTATION OF NUMERIC VALUE USING OVERLAP BITS
A redundant representation is provided where an Mbit value represents a Pbit numeric value using a plurality of Nbit portions, where M>P>N. An anchor value identifies the significance of bits... 

US20170109134 
SYSTEM AND METHOD FOR ROUNDING RECIPROCAL SQUARE ROOT RESULTS OF INPUT FLOATING POINT NUMBERS
Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a... 

US20170046128 
PROCESSING FIXED AND VARIABLE LENGTH NUMBERS
Embodiments of a processor are disclosed for performing arithmetic operations on variablelength and fixedlength machine independent numbers. The processor may include a floating point unit, and... 

US20170031655 
Rounding Floating Point Numbers
Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and... 

US20170010863 
APPARATUS AND METHOD FOR CONTROLLING ROUNDING WHEN PERFORMING A FLOATING POINT OPERATION
An apparatus and method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation,... 

US20160092167 
ROUNDING FLOATING POINT NUMBERS
Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and... 

US20160070538 
Round For Reround Mode In A Decimal Floating Point Instruction
A roundforreround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the... 

US20160070536 
FLOATINGPOINT ARITHMETIC DEVICE, SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM
A floatingpoint arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a... 

US20160011855 
CHECK PROCEDURE FOR FLOATING POINT OPERATIONS
Method and computer system for implementing an operation on ≧1 floating point input, in accordance with a rounding mode, e.g. using a NewtonRaphson technique. The floating point result comprises... 