Matches 1 - 50 out of 63 1 2 >


Match Document Document Title
US20150006597 Optimized Trotterization via Multi-Resolution Analysis  
Operators such as unitary operators common in quantum mechanical applications may be approximated by a Trotter-like approximation. An operator may be decomposed and terms of the operator may be...
US20110302229 CALCULATING LARGE PRECISION COMMON LOGARITHMS  
Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the...
US20130080489 SYSTEMS AND METHODS FOR DETERMINING RESPIRATION INFORMATION FROM A PHOTOPLETHYSMOGRAPH  
A patient monitoring system may receive a photoplethysmograph (PPG) signal including samples of a pulse waveform. A plurality of morphology metric signals may be generated from the PPG signal. The...
US20140280406 SYSTEMS AND METHODS FOR ESTIMATING UNCERTAINTY  
A computer-implemented method includes receiving instructions to execute an analytic, wherein the instructions comprise one or more analytic inputs and a corresponding one or more uncertainty...
US20140207836 Vector Comparator System for Finding a Peak Number  
A comparator (231) for determining a peak number, representing a maximum or minimum of a set of numbers, includes a multi-element comparator (232) for comparing different pages of the set of...
US20110022647 APPARATUS FOR CALCULATING ABSOLUTE DIFFERENCE  
Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference...
US20110010410 SYSTEM FOR CONVERGENCE EVALUATION FOR STATIONARY METHOD ITERATIVE LINEAR SOLVERS  
A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage...
US20110099214 SYSTEM AND METHOD OF USING COMMON ADDER CIRCUITRY FOR BOTH A HORIZONTAL MINIMUM INSTRUCTION AND A SUM OF ABSOLUTE DIFFERENCES INSTRUCTION  
A system which uses common adder circuitry to perform either one of a horizontal minimum instruction and a sum of absolute differences instruction including multiple adders, a sum circuit, a...
US20130238680 DECIMAL ABSOLUTE VALUE ADDER  
A decimal absolute value adder includes a first circuit adding two operands for a first result; a second circuit adding the two operands to 10 for a second result; a third circuit adding the two...
US20120166501 COMPUTATION OF JACOBIAN LOGARITHM OPERATION  
An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of first signals carrying (i) a...
US20140258352 SPACE DILATING TWO-WAY VARIABLE SELECTION  
A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue...
US20090043717 METHOD AND A SYSTEM FOR SOLVING DIFFICULT LEARNING PROBLEMS USING CASCADES OF WEAK LEARNERS  
A method and a system for designing a learning system (30) based on a cascade of weak learners. Every implementation of a cascade of weak learners is composed of a base block (60) and a cascade of...
US20100332572 EXPLOITATION OF TOPOLOGICAL CATEGORIZATION OF CHAOTIC AND FRACTAL FUNCTIONS, INCLUDING FIELD LINE CALCULATIONS  
A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions,...
US20130335853 Pipelined Vectoring-Mode CORDIC  
Various embodiments of the present invention provide pipelined vectoring-mode CORDICS including a coordinate converter operable to yield a converted vector based on an input vector, wherein an x...
US20090063599 FAST COMPUTATION OF PRODUCTS BY DYADIC FRACTIONS WITH SIGN-SYMMETRIC ROUNDING ERRORS  
A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry,...
US20100076723 TENSOR LINEAR LAPLACIAN DISCRIMINATION FOR FEATURE EXTRACTION  
Tensor linear Laplacian discrimination for feature extraction is disclosed. One embodiment comprises generating a contextual distance based sample weight and class weight, calculating a...
US20110137968 METHOD FOR DETERMINING THE POSITION OF IMPACTS  
A method for determining the position of impacts on an object comprising two acoustic sensors, and N active areas of said object, comprises the steps of: (a) receiving two acoustic signals S1(t)...
US20140358978 VECTOR QUANTIZATION WITH NON-UNIFORM DISTRIBUTIONS  
Systems and methods are described for encoding quantized vector parameters in a bitstream are described. An exemplary method may include receiving a vector of integers used in a data compression...
US20080220490 Method for Improving Organisms Using Flux Scanning Based on Enforced Objective Flux  
The present invention relates to a method for improving useful substance-producing organisms using metabolic flux analysis, and more particularly to a method for improving a host organism...
US20080320065 Arithmetic processing apparatus and arithmetic processing method  
In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher...
US20080313248 Arrangement and method for cross-monitoring of data  
An arrangement for cross monitoring two independent signals. The arrangement a calculator configured to calculate a value depending upon a signal value, a drift value and a feedback value, and a...
US20130135481 PHASOR-BASED PULSE DETECTION  
A phasor-based pulse detection system includes a first multiplier stage configured to apply a first delayed conjugate multiplication operation to an input signal. The system can also include a...
US20080235310 Difference degree evaluation device, difference degree evaluation method and program product  
A difference degree evaluation device includes a signal acquisition unit which acquires at least two signals which are objects of matching, a memory unit which stores one of the two signals, which...
US20140297703 SIGNAL RECONSTRUCTION USING TOTAL-VARIATION PRIMAL-DUAL HYBRID GRADIENT (TV-PDHG) ALGORITHM  
A mechanism for reconstructing a signal (e.g., an image) based on a vector s, which includes measurements of the signal. The measurements have been acquired using at least a portion of a...
US20140172932 DEVICE AND METHOD FOR CALCULATING ABSOLUTE AMOUNT OF DISPLACEMENT, AND METHOD FOR SAME  
Some embodiments address a problem of detecting the absolute amount of displacement of a moving body. In various embodiments, the multi-turn absolute angle of rotation of a main shaft is...
US20090063598 APPARATUS AND METHOD FOR CALCULATING AND VISUALIZING TARGETS  
A computer-readable medium includes executable instructions to define a target value, define an achievement boundary range, define specific values for the achievement boundary range, and combine...
US20070271319 Apparatus for an Method of Signal Processing  
A set of related methods of demodulating amplitude and frequency modulated signals. The emphasis is on using an iterative approach to separate an envelope signal and a frequency modulated signal...
US20100042902 ERROR-FLOOR MITIGATION OF ERROR-CORRECTION CODES BY CHANGING THE DECODER ALPHABET  
In one embodiment, an LDPC decoder has one or more reconfigurable adders that generate variable-node messages and one or more reconfigurable check-node units (CNUs) that generate check-node...
US20090049549 APPARATUS AND METHOD FOR DETECTION OF MALICIOUS PROGRAM USING PROGRAM BEHAVIOR  
An apparatus and method of diagnosing whether a computer program executed in a computer system is a malicious program and more particularly, an apparatus and method of diagnosing whether a...
US20080250090 Adaptive filter device and method for determining filter coefficients  
An adaptive filter device, including a finite impulse response (FIR) filter which is based on filter coefficients, which are determined based on a predetermined iterative adaptation algorithm for...
US20090177723 METHOD AND APPARATUS FOR APPROXIMATING AN UPPER-BOUND LIMIT FOR AN ABSOLUTE VALUE OF A COMPLEX NUMBER OR NORM OF A TWO-ELEMENT VECTOR  
A method for approximating an upper bound limit for the absolute value of a complex number or the norm of a two-element vector is disclosed. An upper bound approximation algorithm is used to...
US20140101214 ARITHMETIC OPERATION IN A DATA PROCESSING SYSTEM  
An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently...
US20110022646 PROCESSOR, CONTROL METHOD OF PROCESSOR, AND COMPUTER READABLE STORAGE MEDIUM STORING PROCESSING PROGRAM  
A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value...
US20120121039 DIGITAL FAST CORDIC FOR ENVELOPE TRACKING GENERATION  
Disclosed is a coordinate rotation digital computer (CORDIC) having a maximum value circuit that selects a larger of the first component or the second component. A minimum value circuit selects a...
US20120134685 LOOP FILTER  
A loop filter include: a register that stores a result of arithmetic operation performed on a complex signal and outputs the stored complex signal; a first multiplier that multiplies the complex...
US20140067889 DATAPATH CIRCUIT FOR DIGITAL SIGNAL PROCESSORS  
A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be...
US20110302230 LOW DELAY MODULATED FILTER BANK  
The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and...
US20090112955 Apparatus and method for performing magnitude detection of arthimetic operations  
An apparatus and method is provided comprising processing circuitry, one or more registers and control circuitry. The control circuitry is configured such that it is responsive to a combined...
US20080140741 METHOD FOR USING THE FUNDAMENTAL HOMOTOPY GROUP IN ASSESSING THE SIMILARITY OF SETS OF DATA  
A method for finding sequences of similar data (SDDs), which are similar to a target sequence of digital data, is invented. The method leverages a new category of signatures, called equivalence...
US20140280405 CONVERSION OF A NORMALIZED N-BIT VALUE INTO A NORMALIZED M-BIT VALUE  
A normalized n-bit value is converted into a normalized m-bit value in accordance with a predetermined rounding mode. An initial m-bit value is determined, where the bits of the initial m-bit...
US20100121793 PATTERN GENERATION METHOD, PATTERN GENERATION APPARATUS, AND PROGRAM  
Disclosed is an apparatus that generates automatically a characteristic pattern in time series data by clustering a plurality of time series subsequences generated from the time series data. The...
US20150012577 SIGNAL PROCESSING DEVICE AND METHOD  
The present invention relates to a signal processing device and method. The device receives, from a sensor which measures a physical quantity applied thereto and outputs an accumulated or...
US20140188961 Vectorization Of Collapsed Multi-Nested Loops  
In an embodiment a method of vectorizing a collapsed multi-nested loop includes executing, in a vector unit of a processor, the collapsed loop to obtain a vector of offsets, including for each of...
US20140025715 Neural Signal Processing and/or Interface Methods, Architectures, Apparatuses, and Devices  
Processing a neural signal sequence occurs in accordance with a neural signal spiking model that includes an exponential component (EC) and a polynomial component (PC). The exponential component...
US20130282777 System and Method for a Floating-Point Format for Digital Signal Processors  
An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and...
US20130232182 SIMD SIGN OPERATION  
Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first...
US20100262639 DIGITAL DATA PROCESSOR  
A digital data processor which receives an N-bit input signal from a data source and converts the N-bit input signal into an M-bit output signal, the M-bit being larger than the N-bit. The digital...
US20160350078 EFFICIENT MODULO CALCULATION  
Hardware logic is described which is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising...
US20160179469 APPARATUS AND METHOD FOR PERFORMING ABSOLUTE DIFFERENCE OPERATION  
An apparatus comprises processing circuitry for performing an absolute difference operation for generating an absolute difference value in response to the first operand the second operand. The...
US20160148120 CALCULATION APPARATUS, CALCULATION METHOD, LEARNING APPARATUS, LEARNING METHOD, AND PROGRAM  
A calculation apparatus includes a feature vector acquisition unit for acquiring a feature vector that corresponds to each alternative of a plurality of choice sets; an absolute evaluation...

Matches 1 - 50 out of 63 1 2 >