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US20150213174 REGRESSION SIGNATURE FOR STATISTICAL FUNCTIONAL COVERAGE  
This application discloses a computing system to implement a design verification tool and simulate a circuit design with a regression. The computing system can capture events performed by a...
US20120215516 IR Drop Analysis in Integrated Circuit Timing  
In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the...
US20080294413 PROGRAM PRODUCT SUPPORTING PHASE EVENTS IN A SIMULATION MODEL OF A DIGITAL SYSTEM  
According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one...
US20110218792 Mixed Concurrent And Serial Logic Simulation Of Hardware Designs  
A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second...
US20110178789 RESPONSE CHARACTERIZATION OF AN ELECTRONIC SYSTEM UNDER VARIABILITY EFFECTS  
A method and device for performing a characterization of a description of the composition of an electronic system in terms of components used are disclosed. Performances of the components are...
US20080005709 VERIFICATION OF LOGIC CIRCUITS USING CYCLE BASED DELAY MODELS  
Methods and systems for verifying a logic circuit. In one embodiment, delay models based on clock cycles are developed and incorporated into the logic circuit so that timing considerations may be...
US20090164198 PARALLEL SIMULATION USING AN ORDERED PRIORITY OF EVENT REGIONS  
In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered...
US20070266355 DISTRIBUTED SIMULTANEOUS SIMULATION  
A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at...
US20090043559 Hardware Verification Batch Computing Farm Simulator  
The exemplary embodiments provide a computer implemented method, apparatus, and computer usable program code for calculating the expected behavior of a group of hardware verification test cases....
US20080103750 VERIFICATION USING SIMULTANEOUS AND INDUCTIVE SAT ALGORITHMS  
A simultaneous satisfiability algorithm, or SSAT, allows simultaneous checks to be made efficiently for a number of literals, x1, . . . ,xn whether x1 is true under any satisfying assignments of a...
US20070157133 Circuit network analysis using algebraic multigrid approach  
This application describes techniques for applying an algebraic multigrid method to analysis of circuit networks with irregular and regular circuit patterns. Adaptive processing may be applied to...
US20090030666 Software Entity for the Creation of a Hybrid Cycle Simulation Model  
Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality...
US20090048818 SIMULATION METHOD OF LOGIC CIRCUIT  
A simulation method of a logic circuit is provided. The simulation method includes operations dividing the logic circuit into a plurality of divided circuits, determining the divided circuit...
US20070198239 Event direction detector and method thereof  
Event direction detection method that distinguishes an external event from an internal event and detects a direction of an event, includes the steps of: acting as intermediary of input/output of...
US20080281572 INTEGRATED CIRCUIT (IC) DESIGN METHOD AND METHOD OF ANALYZING RADIATION-INDUCED SINGLE-EVENT UPSETS IN CMOS LOGIC DESIGNS  
A logic design tool, a tool for analyzing soft error sensitivities in logic, and a program product for logic design. A particle generator simulates events likely to occur for a given operating...
US20100256969 GENERATING IMPLICIT LABELS AND TRAINING A TAGGING MODEL USING SUCH LABELS  
A training module is described for training a conditional random field (CRF) tagging model. The training module trains the tagging model based on an explicitly-labeled training set and an...
US20070101302 Mixed signal circuit simulator  
The waveform created by a circuit simulator is selected. The input data 11 inputted by an inputting means are obtained for a point on the waveform or the waveform. The selected waveform and the...
US20100280814 LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS  
Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure...
US20090319253 FPGA Simulated Annealing Accelerator  
Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a...
US20070157135 PARALLEL MULTI-RATE CIRCUIT SIMULATION  
A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions,...
US20090222253 System and Method for Switch-Level Linear Simulation Using Verilog  
A method for rapidly simulating combined analog circuits and digital circuits includes separating the combined circuits into a linear sub-network and logic sub-network. Shared nodes, shared by the...
US20080195367 Clock gating analyzing apparatus, clock gating analyzing method, and computer product  
Clock gating analysis of a target circuit having a plurality of clock gates, involves the calculation of a clock gate function for each of the clock gates. The clock gate functions indicate an...
US20060277020 A reconfigurable system for verification of electronic circuits using high-speed serial links to connect asymmetrical evaluation and canvassing instruction processors  
A reconfigurable scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and...
US20090006068 SOFTWARE EXECUTING DEVICE AND CO-OPERATION METHOD  
There is provided with a software executing device co-operating with a hardware circuit or a hardware simulator, including: a software executing unit configured to execute a software; an execution...
US20060190234 Property generating method, verification method and verification apparatus  
When a property for verifying a logic system is generated, a list of corresponding events is generated from specifications that the logic system should meet, an event of an undefined state in a...
US20090326873 INTEGRATED CIRCUIT DESIGN IN OPTICAL SHRINK TECHNOLOGY NODE  
Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a...
US20050177357 Static timing model for combinatorial gates having clock signal input  
A method of modeling a combinatorial gate which includes providing a data signal input at the combinatorial gate, providing a clock signal input at the combinatorial gate, propagating the clock...
US20080222227 Design Structure for a Booth Decoder  
A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second...
US20060247906 METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS  
A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator...
US20050251767 Processing of circuit design data  
One example embodiment of an approach to circuit design analysis comprises partitioning a circuit design into first, second and boundary parts, the boundary part including circuit portions from...
US20070300194 Film thickness predicting program, recording medium, film thickness predicting apparatus, and film thickness predicting method  
A film thickness predicting apparatus compares a measurement value of a copper plating formed on wiring grooves of various patterns measured using a TEG and a film thickness of the copper plating...
US20090326903 SOFTWARE CONTROLLED LAB-ON-A-CHIP EMULATION  
A software-controlled chemical process emulation system and environment having individually-addressable and/or group-addressable software-controlled chemical system processing modules,...
US20110224965 Modeling Loading Effects of a Transistor Network  
A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that...
US20090024379 EVALUATION DEVICE  
Evaluation by logic simulation can be favorably performed. A target packet determination part determines if a target packet which is a response packet that is to be transmitted with respect to a...
US20060156264 Method and apparatus for supporting verification of system, and computer product  
In a verification support apparatus, an input unit accepts input of an unverified specification description representing an unverified design object constituted by unverified model elements. A...
US20050010460 Facilities control system and method of controlling facilities  
In an aspect of the present invention, a facilities control system includes a simulation section which carries out a simulation of a time change of a status of an object of a target based on a...
US20070256041 Method and apparatus of core timing prediction  
A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any...
US20090240484 SIMULATION APPARATUS, SIMULATION METHOD, AND PROGRAM  
A simulation apparatus that performs simulation of design data of a verification target circuit including a logic circuit that operates as a multi-cycle path of N cycles in synchronization with a...
US20090171646 METHOD FOR ESTIMATING POWER CONSUMPTION  
A method for determining system and software configuration that includes: calculating a power consumption estimate of a modeled system associated with an execution of a certain software code; and...
US20080208557 SIMULATION METHOD AND SIMULATION SYSTEM  
A simulation executing unit 1, an execution list forming unit 2, and an execution list 3 are prepared. The simulation executing unit 1 does not execute all of function models 4 every cycle, but...
US20070074141 Simulation apparatus and simulation method  
According to an aspect of the invention, a simulation apparatus includes: a computer configured to execute a program which is formed as an operating description having no temporal restriction; and...
US20050038640 Method and apparatus for automatically testing the design of a simulated integrated circuit  
A method and apparatus for automatically testing the design of a simulated integrated circuit containing a network of flip-flops. The network is put into a reset state and each flip-flop is tested...
US20050251766 Circuit design interface  
According to an example embodiment of an approach to circuit design processing involves using an interface for retrieving and processing circuit design data for use by a plurality of simulation...
US20090094014 Software System For Binding Model Data To View Components  
A flexible method of mapping view components to data model objects in an object oriented system. The mapping manages navigating the data model graph to access data needed by the view component and...
US20080127006 Real-Time Data Stream Decompressor  
Method, system, and program product for expanding the effective capacity of embedded memory by storing data in a compressed form and reading the data out with subsequent data decompression,...
US20080228461 Method of Simulating a Complex System Including Scheduler Hierarchy, and Corresponding Storage Means and Computer Program Product  
A method is provided for simulating a complex system including a scheduler hierarchy. The complex system includes at least one processor that executes a set of functions under the control of a...
US20080262819 Programmable Logic Array for Schedule-Controlled Processing  
The electronic data processing circuit targets the emulation of a logic function. The circuit includes a single clock providing time unit signals, a programmable synchronous logic array for...
US20060277509 SYSTEM AND METHOD FOR ANALYZING POWER CONSUMPTION OF ELECTRONIC DESIGN UNDERGOING EMULATION OR HARDWARE BASED SIMULATION ACCELERATION  
The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to...
US20100070257 Methods, Systems, and Computer Program Products for Evaluating Electrical Circuits From Information Stored in Simulation Dump Files  
Disclosed are methods, systems, and computer program products for evaluating performance aspects of electrical circuits, and particularly digital logic circuits. An exemplary method comprises...
US20060080626 Visualization method and apparatus for logic verification and behavioral analysis  
A logic verification tool detects and flags a logic operation with high probability to cause a fault in an electronic system. An efficient logic debug method utilizes a partial sequence of signal...

Matches 1 - 50 out of 67 1 2 >