Matches 1 - 39 out of 39


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US20070219771 Branching and Behavioral Partitioning for a VLIW Processor  
In one aspect, the present invention overcomes the limitations of the prior art by provident a logic simulation ;system that uses a VLIW simulation processor with many parallel processor elements...
US20070129926 Hardware acceleration system for simulation of logic and memory  
A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in...
US20090006066 Method and System for Automatic Selection of Test Cases  
A system for selecting a test case. A test case with a high score is selected. A simulation job is run on a device under test on a plurality of processors using the selected test case. Simulation...
US20110270599 METHOD FOR TESTING INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE  
A method for testing an integrated circuit includes simulating the integrated circuit and generating waveforms of signals at a plurality of nodes of the integrated circuit, generating a text file...
US20100250224 POWER SOURCE NOISE ANALYSIS DEVICE AND ANALYSIS METHOD  
A power source noise analysis device includes an analysis portion. The analysis portion estimates an internal impedance of a semiconductor chip being an object to be analyzed based on a power...
US20070156380 Logic event simulation  
A parallel processor for a logic event simulation (APPLES) including a main processor and an associative memory mechanism including a response resolver. Further, the associative memory mechanism...
US20130282352 REAL TIME LOGIC SIMULATION WITHIN A MIXED MODE SIMULATION NETWORK  
Technologies relating to real time logic simulation within a mixed mode simulation network are described. Mixed mode simulation networks may comprise Boolean Processing Units (BPUs) and Real Time...
US20150356220 AUTOMATED INPUT SIMULATION FOR SIMULATED PROGRAMMABLE LOGIC CONTROLLER  
Input simulation is provided (36) as part of simulating (38) a programmable logic controller. The simulator program itself includes a graphic user interface for the user to configure a sequence of...
US20050192789 Methods for formal verification on a symbolic lattice domain  
Methods for formal verification of circuits and other finite-state systems are disclosed. Formal definitions and semantics are disclosed for a model of a finite-state system, an assertion graph to...
US20080306722 Logic verification system  
There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge...
US20150227661 COMPUTER PRODUCT, SIMULATION APPARATUS, SIMULATION METHOD, BUS MODEL, AND BUS CIRCUIT  
A non-transitory, computer-readable recording medium stores therein a simulation program that causes a computer to execute a process that includes obtaining an architecture model that includes a...
US20050119870 Processor system with execution-reservable accelerator  
A processor system capable of performing high-speed image processing is provided. The processor system includes a CPU and an accelerator. The CPU connected to the accelerator issues reservations...
US20080184150 ELECTRONIC CIRCUIT DESIGN ANALYSIS TOOL FOR MULTI-PROCESSOR ENVIRONMENTS  
One or more technologies described herein can be used for viewing results of a simulation of a software executable in a multi-processor electronic circuit design. A debug environment can display...
US20060190234 Property generating method, verification method and verification apparatus  
When a property for verifying a logic system is generated, a list of corresponding events is generated from specifications that the logic system should meet, an event of an undefined state in a...
US20090259453 Method of modeling SRAM cell  
A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The...
US20060253271 Method for facilitating transformation of multi-threaded process-oriented object code to event-based object code  
A method comprises analyzing multi-threaded process-oriented object code representing a simulation model and transforming said multi-threaded process-oriented object code to event-based object...
US20080288231 Apparatus and method for cooperation verification  
A cooperation verifying apparatus includes a storage unit and a processing unit. The processing unit simulates a software-based portion and a hardware-based portion in a target system, issues...
US20080071514 Apparatus for handling register-transfer-level description, method thereof, and program storage medium storing program thereof  
A circuit description is separated into sequential-circuit descriptions as a sequential-circuit-description part and combinational-circuit descriptions as a combinational-circuit-description part....
US20070255547 SOLVING THE PERIODIC STEADY-STATE OPERATING CONDITION OF A PHASE-LOCKED LOOP OR DELAY-LOCKED LOOP CIRCUIT USING A TRANSIENT ESTIMATION METHOD  
A system and method for quickly determining the steady-state condition of a phase-locked loop or a delay-locked loop circuit by simulating a phase-locked loop in DC transient and periodic...
US20070233448 Detecting computer system simulation errors  
Validating simulation models. A computing environment includes a performance scenario of a system. The performance scenario includes device models defining device behavior and/or capacity. The...
US20140149100 METHOD FOR CHARACTERIZING THE SENSITIVITY OF AN ELECTRONIC COMPONENT FOR A METHOD FOR DESIGNING ELECTRONIC EQUIPMENT  
A method for designing electronic equipment comprising at least one electronic component. The component executes a dynamic application and is subjected to disruptions. The software application...
US20120296623 MACHINE TRANSPORT AND EXECUTION OF LOGIC SIMULATION  
A processing architecture and methods are disclosed in which a simulation state vector can be contained in a common memory, formatted in a known form, distributed in a deterministic bus to a sea...
US20120046931 MULTIPLE POWER-SUPPLY SIMULATION RESULT ANALYZER AND METHOD OF ANALYZING THE SAME  
In a method of displaying a waveform of a simulation result, a waveform file extractor which extracts information of voltage values in addition to simulation times, values, and signal names input...
US20090144044 Logic simulator and logic simulation method  
A logic simulator includes a storage device and a simulator part. The storage device stores a signal duration delay file which associates first signal duration information indicating duration of...
US20090055010 Back annotation equipment, mask layout correcting equipment, back annotation method, program, recording medium, process for fabricating semiconductor integrated circuit  
The present invention provides a back annotation apparatus for determining the delay value of a logic cell used in a timing simulation in view of the changes in the properties of a transistor...
US20160217239 METHOD AND SYSTEM FOR SELECTING STIMULATION SIGNALS FOR POWER ESTIMATION  
A power estimation signal selection tool identifies the signals of an IC design that should be captured in waveform data and activity formats during simulation or emulation. The power estimation...
US20160063158 METHOD AND DEVICE FOR SIMULATING A CIRCUIT DESIGN  
The present invention discloses a method and device for simulating a circuit design. The method includes identifying at least one Sequential-cell-To-Sequential-cell (S2S) block in the circuit...
US20120290282 REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES  
A logic simulation program, method and system for obtaining a set of reachable states for a logic design that can be used to provide input to other algorithms that simplify the netlist describing...
US20100305934 LOGICAL SIMULATION SYSTEM, LOGICAL SIMULATION METHOD, AND LOGICAL SIMULATION PROGRAM  
A program that simulates a netlist data including a plurality of basic elements using a computer includes a logic operation section configured to stipulate a logic operation of at least one of the...
US20100174521 DATA PROCESSING WITH CIRCUIT MODELING  
Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification...
US20140278329 Modeling Content-Addressable Memory For Emulation  
Aspects of the invention relate to techniques for modeling content-addressable memory for emulation. An emulation device according to various embodiments of the invention comprises one or more...
US20100305933 Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution  
A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe...
US20090300558 USE OF STATE NODES FOR EFFICIENT SIMULATION OF LARGE DIGITAL CIRCUITS AT THE TRANSISTOR LEVEL  
A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the...
US20050049845 Verification and characterization of noise margin in integrated circuit designs  
In accordance with the present invention there is provided a method of simulating a memory circuit design in order to verify the signal strength of bit lines. The method begins by identifying...
US20140236563 INTEGRATED CIRCUIT SIMULATION METHOD AND SYSTEM  
Provided is an integrated circuit simulation method. The simulation time points of the entire circuit are divided into a plurality of independent simulation time windows, and according to a logic...
US20120265515 METHOD AND SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ACCELERATING SIMULATIONS  
Method, system, and computer program product. The method may include: receiving a model of a circuit that includes logic that is designed to receive sequence information and/or constants from...
US20070244685 METHOD FOR MODELING METASTABILITY DECAY USING FENCE LOGIC INSERTION  
A method for modeling metastablilty decay in digital circuit devices includes identifying each latch at a receiving end of an asynchronous clock boundary, enumerating a latch depth for each latch...
US20110295584 VERIFICATION SUPPORT PROGRAM, LOGIC VERIFICATION DEVICE, AND VERIFICATION SUPPORT METHOD  
A computer-readable recording medium configured to store a verification support program, the program causing a computer to execute logic verification operations for a system including a plurality...
US20110238400 DEVICE FOR A METHOD OF MODELLING A PHYSICAL STRUCTURE  
A device (100) for modelling a physical structure by a number of finite state machines comprising a simulation unit (114) adapted for simulating the physical structure by a number of finite state...

Matches 1 - 39 out of 39