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US20140236563 
INTEGRATED CIRCUIT SIMULATION METHOD AND SYSTEM
Provided is an integrated circuit simulation method. The simulation time points of the entire circuit are divided into a plurality of independent simulation time windows, and according to a logic... 

US20080027701 
Printed Circuit Board Design Instruction Support Method and Device
There are provided a printed circuit board design instruction support method between a circuit design and a printed circuit board design, a printed circuit board design instruction support device... 

US20120053924 
SYSTEM AND METHOD FOR EXECUTING FUNCTIONAL SCANNING IN AN INTEGRATED CIRCUIT ENVIRONMENT
An example method is provided and includes executing a functional test for an integrated circuit and observing a failure associated with the integrated circuit. The method also includes executing... 

US20120046931 
MULTIPLE POWERSUPPLY SIMULATION RESULT ANALYZER AND METHOD OF ANALYZING THE SAME
In a method of displaying a waveform of a simulation result, a waveform file extractor which extracts information of voltage values in addition to simulation times, values, and signal names input... 

US20120278057 
PHYSICAL REALIZATIONS OF A UNIVERSAL ADIABATIC QUANTUM COMPUTER
Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled... 

US20110054876 
PHYSICAL REALIZATIONS OF A UNIVERSAL ADIABATIC QUANTUM COMPUTER
Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled... 

US20090307637 
METHOD OF DESIGNING MULTISTATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWERMANAGED FUNCTIONAL BLOCK
Methods of designing and testing restore logic for restoring values to storage elements of powermanaged logic circuitry. In one implementation, a design method disclosed includes providing a... 

US20080071514 
Apparatus for handling registertransferlevel description, method thereof, and program storage medium storing program thereof
A circuit description is separated into sequentialcircuit descriptions as a sequentialcircuitdescription part and combinationalcircuit descriptions as a combinationalcircuitdescription part.... 

US20110295584 
VERIFICATION SUPPORT PROGRAM, LOGIC VERIFICATION DEVICE, AND VERIFICATION SUPPORT METHOD
A computerreadable recording medium configured to store a verification support program, the program causing a computer to execute logic verification operations for a system including a plurality... 

US20120265515 
METHOD AND SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ACCELERATING SIMULATIONS
Method, system, and computer program product. The method may include: receiving a model of a circuit that includes logic that is designed to receive sequence information and/or constants from... 

US20090106010 
TECHNIQUE FOR DIGITAL CIRCUIT FUNCTIONALITY RECOGNITION FOR CIRCUIT CHARACTERIZATION
A method and system of digital circuit functionality recognition for circuit characterization is disclosed. In one embodiment, a method for determining the valid arcs includes receiving a truth... 

US20110161066 
DELTA RETIMING IN LOGIC SIMULATION
Aspects of the present invention are directed to improving the speed of eventdriven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is... 

US20100004904 
DISPLAY DESIGNING SYSTEM AND METHOD FOR DESIGNING A DISPLAY
A display designing system and a method thereof. The display designing system includes a variety of operation modules and an integration module. After receiving initial parameters and selecting... 

US20100094610 
Circuit simulation model generation apparatus, circuit simulation model generation method and circuit simulation apparatus
A circuit simulation model generation apparatus includes: a power supply wiring model generation section that generates a power supply wiring model which is a model of the power supply wiring; a... 

US20090063121 
OPTIMIZATION OF DISPLAYED RF COVERAGE
A method for optimizing RF coverage includes dividing a floor plan according to a plurality of grids. Radio frequency coverage for each of the plurality of grids is calculated to render a... 

US20090254331 
COMPACT CIRCUITSIMULATION OUTPUT
Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary... 

US20080306722 
Logic verification system
There is provided a logic verification system having improved development time and design quality, in which all pins of an FPGA module are wired in direct between the FPGA module and a bridge... 

US20100076742 
SIMULATION MODEL FOR TRANSISTORS
Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model. 

US20080071513 
Test generation for low power circuits
In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and... 

US20090164197 
METHOD FOR TRANSFORMING OVERLAPPING PATHS IN A LOGICAL MODEL TO THEIR PHYSICAL EQUIVALENT BASED ON TRANSFORMATION RULES AND LIMITED TRACEABILITY
A method for transforming paths in a logical model to their physical equivalent in a physical model is provided. A logical model is retrieved. All entities in the logical model are mapped. All... 

US20100318952 
System and Method Incorporating An Arithmetic Logic Unit For Emulation
A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed... 

US20100324881 
SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS
A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method... 

US20080040637 
DIAGNOSING MIXED SCAN CHAIN AND SYSTEM LOGIC DEFECTS
Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system... 

US20070255547 
SOLVING THE PERIODIC STEADYSTATE OPERATING CONDITION OF A PHASELOCKED LOOP OR DELAYLOCKED LOOP CIRCUIT USING A TRANSIENT ESTIMATION METHOD
A system and method for quickly determining the steadystate condition of a phaselocked loop or a delaylocked loop circuit by simulating a phaselocked loop in DC transient and periodic... 

US20070233448 
Detecting computer system simulation errors
Validating simulation models. A computing environment includes a performance scenario of a system. The performance scenario includes device models defining device behavior and/or capacity. The... 

US20080243462 
INSTRUCTION ENCODING IN A HARDWARE SIMULATION ACCELERATOR
A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the... 

US20080294411 
Systems and Methods for Logic Verification
Methods and systems for simulating logic may translate logic design into executable code for a multiprocessor based parallel logic simulation device. A system may implement one or more parallel... 

US20130282352 
REAL TIME LOGIC SIMULATION WITHIN A MIXED MODE SIMULATION NETWORK
Technologies relating to real time logic simulation within a mixed mode simulation network are described. Mixed mode simulation networks may comprise Boolean Processing Units (BPUs) and Real Time... 

US20120290282 
REACHABILITY ANALYSIS BY LOGICAL CIRCUIT SIMULATION FOR PROVIDING OUTPUT SETS CONTAINING SYMBOLIC VALUES
A logic simulation program, method and system for obtaining a set of reachable states for a logic design that can be used to provide input to other algorithms that simplify the netlist describing... 

US20060253271 
Method for facilitating transformation of multithreaded processoriented object code to eventbased object code
A method comprises analyzing multithreaded processoriented object code representing a simulation model and transforming said multithreaded processoriented object code to eventbased object... 

US20070244685 
METHOD FOR MODELING METASTABILITY DECAY USING FENCE LOGIC INSERTION
A method for modeling metastablilty decay in digital circuit devices includes identifying each latch at a receiving end of an asynchronous clock boundary, enumerating a latch depth for each latch... 

US20090182545 
Simulating an Operation of a Digital Circuit
A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01)... 

US20080126066 
Method for Modeling an HDL Design Using Symbolic Simulation
A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary... 

US20090240483 
SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC LOGIC MODEL BUILD PROCESS WITH AUTONOMOUS QUALITY CHECKING
A computer program product stored including machine executable instructions stored on machine readable media, the instructions configured for performing automatic logic build processes and... 

US20050192789 
Methods for formal verification on a symbolic lattice domain
Methods for formal verification of circuits and other finitestate systems are disclosed. Formal definitions and semantics are disclosed for a model of a finitestate system, an assertion graph to... 

US20090171645 
LOGIC SIMULATOR AND LOGIC SIMULATION METHOD
According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in... 

US20090006066 
Method and System for Automatic Selection of Test Cases
A system for selecting a test case. A test case with a high score is selected. A simulation job is run on a device under test on a plurality of processors using the selected test case. Simulation... 

US20060190234 
Property generating method, verification method and verification apparatus
When a property for verifying a logic system is generated, a list of corresponding events is generated from specifications that the logic system should meet, an event of an undefined state in a... 

US20090144044 
Logic simulator and logic simulation method
A logic simulator includes a storage device and a simulator part. The storage device stores a signal duration delay file which associates first signal duration information indicating duration of... 

US20100138710 
LOGIC VERIFICATION APPARATUS
To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A... 

US20080201128 
Method and System for Performing Ternary Verification
A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary... 

US20090055010 
Back annotation equipment, mask layout correcting equipment, back annotation method, program, recording medium, process for fabricating semiconductor integrated circuit
The present invention provides a back annotation apparatus for determining the delay value of a logic cell used in a timing simulation in view of the changes in the properties of a transistor... 

US20050119870 
Processor system with executionreservable accelerator
A processor system capable of performing highspeed image processing is provided. The processor system includes a CPU and an accelerator. The CPU connected to the accelerator issues reservations... 

US20090132221 
Verification of Highly Optimized Synchronous Pipelines via Random Simulation Driven by Critical Resource Scheduling System and Program Product
Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating... 

US20080126065 
System and Method for Improved Logic Simulation Using a Negative Unknown Boolean State
A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial... 

US20100305933 
Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution
A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe... 

US20080255821 
CONTROLLING OPERATION OF A DIGITAL SYSTEM UTILIZING REGISTER ENTITIES
In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and... 

US20080294412 
DESIGN STRUCTURE FOR PERFORMING CACHELINE POLLING UTILIZING STORE WITH RESERVE AND LOAD WHEN RESERVATION LOST INSTRUCTIONS
A design structure for performing cacheline polling utilizing store and reserve and load when reservation lost instructions is disclosed. In one embodiment a method is provided which comprises... 

US20110238400 
DEVICE FOR A METHOD OF MODELLING A PHYSICAL STRUCTURE
A device (100) for modelling a physical structure by a number of finite state machines comprising a simulation unit (114) adapted for simulating the physical structure by a number of finite state... 

US20080133205 
TESTING THE COMPLIANCE OF A DESIGN WITH THE SYNCHRONIZATION REQUIREMENTS OF A MEMORY MODEL
A method for compliance testing of a circuit design that includes at least one processor and a memory includes defining a memory model. The memory model includes synchronization mechanisms for... 