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US20080221851 |
Aid design system for analog integrated circuit and the method thereof
The aid design system for analog ICs includes an analog IC database, a peripheral component database, an input module, a computing simulation module, a selection module and an output module. The... |
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US20130124182 |
RETRIEVING ODD NET TOPOLOGY IN HIERARCHICAL CIRCUIT DESIGNS
According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very... |
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US20140005999 |
TEST BENCH TRANSACTION SYNCHRONIZATION IN A DEBUGGING ENVIRONMENT
This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to... |
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US20120053913 |
Electrical-Thermal Co-Simulation with Joule Heating and Convection Effects for 3D Systems
In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least... |
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US20120072876 |
METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULATION AND VERIFICATION
Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a... |
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US20120330637 |
METHOD FOR PROVIDING DEBUGGING TOOL FOR A HARDWARE DESIGN AND DEBUGGING TOOL FOR A HARDWARE DESIGN
A method is provided for providing a debugging tool for a hardware design specified in a hardware description language. The method includes receiving one or multiple source files of the specified... |
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US20120089383 |
METHODS AND SYSTEMS FOR PERFORMING TIMING SIGN-OFF OF AN INTEGRATED CIRCUIT DESIGN
Systems and methods for performing timing sign-off of an integrated circuit design are disclosed. In one example embodiment the integrated circuit design is divided into plurality of blocks based... |
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US20120084745 |
Design Method for Non-Shrinkable IP Integration
A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first... |
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US20120150522 |
CONVERSION OF CIRCUIT DESCRIPTION TO AN ABSTRACT MODEL OF THE CIRCUIT
A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the... |
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US20130054218 |
Method and Software Tool for Automatically Testing a Circuit Design
A software tool and method for performing a simulation of a circuit to automatically test a circuit design are disclosed. A series of primary transactions may be performed on the circuit under... |
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US20110191093 |
SYSTEM AND METHOD OF GENERATING EQUATION-LEVEL DIAGNOSTIC ERROR MESSAGES FOR USE IN CIRCUIT SIMULATION
A mechanism for providing equation-level diagnostic error messages for system models undergoing circuit simulations is discussed. The components in a model of a system being simulated are... |
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US20140095140 |
BIAS-TEMPERATURE INSTABILITY RELIABILITY CHECKS BASED ON GATE VOLTAGE THRESHOLD FOR RECOVERY
A method of determining a saturation current degradation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation... |
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US20110276321 |
DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE
A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum... |
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US20130018644 |
System and Method For Controlling Granularity of Transaction Recording In Discrete Event Simulation
A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is... |
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US20110107293 |
SIMULATION-BASED DESIGN STATE SNAPSHOTTING IN ELECTRONIC DESIGN AUTOMATION
Some embodiments provide a system that performs a simulation within an electronic design automation (EDA) application. During operation, the system obtains a design from a user of the EDA... |
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US20110144968 |
SIMULATION PARAMETER EXTRACTING METHOD OF MOS TRANSISTOR
A simulation parameter extracting method of a MOS transistor according to an exemplary aspect of the present invention includes evaluating a measured value that includes a true gate-overlap... |
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US20140088948 |
REDUCING REPEATER POWER
A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original... |
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US20130275110 |
REDUCING REPEATER POWER
A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original... |
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US20110071812 |
Small-Signal Stability Analysis at Transient Time Points of Integrated Circuit Simulation
Simulation method and system for analyzing the stability of a modeled electronic circuit. Simulation of the transient response to a desired input stimulus is performed in a piece-wise fashion, in... |
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US20150006139 |
HEAT DISSIPATION SIMULATOR
A heat dissipation simulator of a component on a printed circuit board (PCB) includes a simulation board and a simulated heat source. The simulation board includes an iron layer and a plastic... |
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US20110257943 |
NODE-BASED TRANSIENT ACCELERATION METHOD FOR SIMULATING CIRCUITS WITH LATENCY
When modeling a circuit, transient analysis is an important part of the analysis. However, for transient analyses, device model evaluating can consume a considerable amount of time, when using... |
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US20150040086 |
METHOD AND SYSTEM FOR REPRODUCING PROTOTYPING FAILURES IN EMULATION
A method for simulating a circuit includes running a first prototype of the circuit a predetermined number of cycles behind a second prototype of the circuit, and running a hardware emulator of... |
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US20100324878 |
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING HOTSPOT DETECTION, REPAIR, AND OPTIMIZATION OF AN ELECTRONIC CIRCUIT DESIGN
Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines,... |
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US20120316857 |
Method for Circuit Simulation
A computer-implemented method for simulating an electrical circuit. The method includes (a) setting a first temperature distribution in the electrical circuit, (b) performing an electrical... |
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US20110288825 |
METHOD AND SYSTEM FOR EQUIVALENCE CHECKING
As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change... |
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US20120278056 |
Characterizing Performance of an Electronic System
In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation... |
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US20100332207 |
VIA IMPEDANCE MATCHING METHOD
A via impedance matching method is provided. Firstly, a circuit model of a via in the PCB is created, which comprises a low pass filter circuit composed of two capacitors connected in parallel and... |
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US20130158972 |
Automated Recovery System Verification
Disclosed are various embodiments for simulating distribution electric circuit models containing simulated software intelligent electronic devices. The distribution circuit and intelligent... |
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US20120143583 |
SYSTEM-LEVEL EMULATION/VERIFICATION SYSTEM AND SYSTEM-LEVEL EMULATION/VERIFICATION METHOD
A system-level emulation/verification system includes an operating device for using a simulator to set soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design... |
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US20100332206 |
METHOD FOR SIMULATING LEAKAGE DISTRIBUTION OF INTEGRATED CIRCUIT DESIGN
A method is provided for simulating leakage distribution of integrated circuit design. The method analyzes a layout of the integrated circuit design to understand the groups of dimensions of the... |
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US20110191092 |
PARALLEL SIMULATION USING MULTIPLE CO-SIMULATORS
A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective... |
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US20120095746 |
NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW
A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In... |
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US20110313749 |
CIRCUIT CONSTANT ANALYSIS METHOD AND CIRCUIT SIMULATION METHOD OF EQUIVALENT CIRCUIT MODEL OF MULTILAYER CHIP INDUCTOR
The occurrence of errors between circuit design using a circuit simulator and the actual circuit performance is quite adequately suppressed. Mutual inductance (Lm) between direct current... |
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US20140236562 |
Resource Mapping in a Hardware Emulation Environment
A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a... |
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US20120253775 |
Multidimensional Monte-Carlo Simulation for Yield Prediction
An embodiment includes a computer program product for providing a yield prediction. The computer program product has a non-transitory computer readable medium with a computer program embodied... |
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US20140100837 |
INTEGRATION VERIFICATION SYSTEM
A verification system for an integrated device includes a plurality of detailed subsystem virtual prototypes, a plurality of fast subsystem virtual prototypes, and a test controller. The plurality... |
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US20110012426 |
POWER SUPPLY SYSTEM AND METHOD
A power supply system includes a power supply, a daughterboard, and a motherboard. Output currents of power connectors of the motherboard and impedances of copper foils between every two adjacent... |
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US20150019194 |
METHOD FOR AUTOMATIC DESIGN OF AN ELECTRONIC CIRCUIT, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT
A method for automatic design of a circuit evaluates thermal effects and electrical effects in a coupled way. A description of the circuit is obtained in terms of a list of simulator nodes or... |
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US20060271345 |
Debugging a circuit using a circuit simulation verifier
A circuit is tested using a device under test, a circuit simulator, and a circuit simulation verifier. Executing the verifier drives the simulator and collects trace information. This trace... |
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US20150032437 |
SYSTEM LEVEL SIMULATION IN NETWORK ON CHIP ARCHITECTURE
Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC... |
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US20140095138 |
CHECKING FOR HIGH BACK-BIAS IN LONG GATE-LENGTH, HIGH TEMPERATURE CASES
A method for checking for reliability problems includes simulating a circuit having at least one MOS transistor that includes a first MOS transistor. Based on the results of this simulation of the... |
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US20110257954 |
Versatile Method and Tool for Simulation of Aged Transistors
In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified... |
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US20130246015 |
Electronic Circuit Simulation Method With Adaptive Iteration
In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method,... |
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US20110307234 |
CIRCUIT SIMULATION METHOD AND CIRCUIT SIMULATION DEVICE
The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage... |
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US20120290281 |
TABLE-LOOKUP-BASED MODELS FOR YIELD ANALYSIS ACCELERATION
In one embodiment, the invention is a method and apparatus for table-lookup-based models for yield analysis acceleration. One embodiment of a method for statistically evaluating a design of an... |
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US20070083351 |
Integrated circuit test simulator
A method and a simulator for testing an electronic circuit by parallel execution of a program in the circuit and in a simulator, including a step of checking that commands and conditions contained... |
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US20090216359 |
PRUNING-BASED VARIATION-AWARE DESIGN
For application to analog, mixed-signal, and custom digital circuits, a system and method to begin with a complex problem description that encompasses many variables from statistical... |
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US20110307235 |
EQUIVALENT CIRCUIT MODEL FOR MULTILAYER CHIP CAPACITOR, CIRCUIT CONSTANT ANALYSIS METHOD, PROGRAM, DEVICE, AND CIRCUIT SIMULATOR
Improved equivalent circuits and circuit analysis using the same for a multiplayer capacitor are provided. In one aspect, the equivalent series capacitance C and part of the equivalent series... |
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US20090112554 |
Test Bench, Method, and Computer Program Product for Performing a Test Case on an Integrated Circuit
The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing... |
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US20110054856 |
Equivalent Device Statistical Modeling for Bitline Leakage Modeling
Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a... |