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US20110208468 POWER DISTRIBUTION NETWORK ESTIMATION DEVICE  
A device that estimates a positional relationship between loads individually connected through sensors to electric power-supply ends provided in a power distribution network includes a...
US20110148428 METHOD FOR MONITORING INSULATION FAULTS IN AN ELECTRIC NETWORK AND VEHICLE COMPRISING AN INSULATION FAULT MONITOR  
A method for monitoring an insulation fault in an electric network with at least one electric power system supplying electric power to one or more electric loads, and at least one insulation...
US20140172346 SYSTEMS AND METHODS FOR PERFORMING REDUNDANCY TESTS ON TURBINE CONTROLS  
A computing device for use in performing a redundancy test on a turbine assembly and a turbine control system including a plurality of controllers each configured to independently control...
US20100042352 PLATFORM SPECIFIC TEST FOR COMPUTING HARDWARE  
A platform specific test for computing hardware and method using same, wherein the method supplies a plurality of test procedures, and provides a computing device to be evaluated, where the...
US20100082282 REDUCTION OF THE NUMBER OF INTEROPERABILITY TEST CANDIDATES AND THE TIME FOR INTEROPERABILITY TESTING  
Provided are a method, system, and article of manufacture wherein a determination is made of a subset of all possible interoperable combinations of components of a computing system, wherein the...
US20070276623 Semiconductor Component Test Process and a System for Testing Semiconductor Components  
A test system can be used for testing semiconductor components, with which several different semiconductor component tests can be performed in succession. A test apparatus receives a test result...
US20120185201 AUTOMATIC POWER SUPPLY TESTING SYSTEM AND METHOD  
An automatic power supply testing system records a preset test order of first and second power supplies with a recording module. The automatic power supply testing system controls a first control...
US20140024145 METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE VOLTAGE BINNING DISPOSITION  
Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast...
US20120041706 TESTING SYSTEM FOR PORTABLE ELECTRONIC DEVICE  
A testing system for a portable electronic device includes a sequential control card, a plurality of test devices, and a plurality of switches. The sequential control card provides and outputs...
US20090299677 CIRCUIT CARD ASSEMBLY TESTING SYSTEM FOR A MISSILE AND LAUNCHER TEST SET  
The invention generally relates to a circuit card assembly testing system for testing and troubleshooting new and failed circuit card assemblies. Specifically, circuit card assemblies that are...
US20080071513 Test generation for low power circuits  
In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and...
US20080133166 Automatic testing method to be used by an IC testing system equipped with multiple testing sites  
An automatic testing method to be used by an IC testing system equipped with multiple testing sites. In this method the testing procedural information for each IC is stored in different sets of...
US20090216480 DEVICE UNDER TEST DE-EMBEDDING  
A method of determining the intrinsic electrical characteristics of a device under test (DUT) includes determining a set of test measurements for a test structure including the device and...
US20080120058 MULTI-CPU MOBILE TERMINAL AND MULTI-CPU TEST SYSTEM AND METHOD  
A mobile terminal equipped with multiple CPUs and a system and method for testing multiple CPUs of the mobile terminal are provided. A mobile terminal of the present invention includes test ports...
US20130132023 STRUCTURE FOR CHARACTERIZING THROUGH-SILICON VIAS AND METHODS THEREOF  
An integrated circuit device can include a number of test structures, whereby each test structure includes a TSV and a plurality of devices-under-test (DUTs). Each of the DUTs in a test structure...
US20080059105 MEMORY-DAUGHTER-CARD-TESTING APPARATUS AND METHOD  
A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing...
US20060195288 Method for at speed testing of multi-clock domain chips  
A method of and system for testing multi clock domain devices at functional clock speed by aligning the Launching C2 clocks of the high speed and low speed domains, issuing a Cl->C2 clock in each...
US20080221824 TEST APPARATUS, TEST METHOD AND RECORDING MEDIUM  
There is provided a test apparatus for testing a plurality of DUTs. The test apparatus includes a plurality of test modules that are connected to the plurality of DUTs and test the plurality of...
US20060085155 Methods and apparatus for local outlier detection  
A method and apparatus for data analysis according to various aspects of the present invention is configured to identify statistical outliers in test data for components, including local outliers...
US20150253379 SYSTEM AND METHOD FOR CLOUD TESTING AND REMOTE MONITORING OF INTEGRATED CIRCUIT DEVICES  
In a system and method for cloud testing and remote monitoring of IC devices on a computerized test platform, the computerized test platform sends to a cloud server unit, which stores test...
US20140074422 ADAPTIVE POWER CONTROL USING TIMING CANONICALS  
A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is...
US20080285636 CALIBRATING JITTER  
Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the...
US20080133165 TEST APPARATUS AND DEVICE INTERFACE  
The test apparatus includes: a plurality of test modules that transmit/receive signals to/from the plurality of DUTs; a test head on which the plurality of test modules are placed; a plurality of...
US20060149493 Method and system for calibrating a light emitting device display  
A method and system for calibrating a light emitting device display is provided. The display includes a plurality of pixel circuits, each having a light emitting device. The system for the...
US20120278027 SYSTEM FOR PERFORMING ELECTRICAL CHARACTERIZATION OF ASYNCHRONOUS INTEGRATED CIRCUIT INTERFACES  
An integrated circuit with a single-channel input/output (I/O) interface and a multi-channel I/O interface includes functional circuits that operate in different clock domains and a test circuit....
US20100036637 METHODS AND APPARATUS FOR HYBRID OUTLIER DETECTION  
Methods and apparatus for data analysis according to various aspects of the present invention are configured to identify statistical outliers in test data for components, including hybrid outliers...
US20150219715 METHODS AND DEVICES FOR THE COMPUTER-AIDED DETERMINATION OF DEVIATION PATTERNS DURING THE PRODUCTION AND/OR TESTING OF A MULTIPLICITY OF DIES AND COMPUTER PROGRAM PRODUCTS  
In various embodiments, a method for the computer-aided determination of deviation patterns during at least one of the production or testing of a multiplicity of dies is provided. The dies are...
US20140244203 TESTING SYSTEM AND METHOD OF INTER-INTEGRATED CIRCUIT BUS  
A testing system configured to test real-time signals of an I2C bus of a motherboard includes an oscillograph and a testing device. The motherboard comprises an I2C master control device and an...
US20110131000 CHIP TESTER, METHOD FOR PROVIDING TIMING INFORMATION, TEST FIXTURE SET, APPARATUS FOR POST-PROCESSING PROPAGATION DELAY INFORMATION, METHOD FOR POST-PROCESSING DELAY INFORMATION, CHIP TEST SET UP AND METHOD FOR TESTING DEVICES UNDER TEST  
A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing...
US20110295543 PERFORMANCE IMPROVEMENT FOR A MULTI-CHIP SYSTEM VIA KERF AREA INTERCONNECT  
A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf...
US20120150476 METHODS OF MONITORING ELECTRONIC DISPLAYS WITHIN A DISPLAY NETWORK  
Methods of monitoring one or more electronic displays are disclosed. A method may include performing at least one diagnostic operation on at least one electronic display having at least one...
US20110288808 OPTIMAL TEST FLOW SCHEDULING WITHIN AUTOMATED TEST EQUIPMENT FOR MINIMIZED MEAN TIME TO DETECT FAILURE  
The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block...
US20090150112 SCAN METHOD AND SYSTEM OF TESTING CHIP HAVING MULTIPLE CORES  
A method of testing chips for manufacturing defects or operational based defects. The method may be used with any chip having logically function elements, including chips having multiple cores...
US20100106449 METHOD TO EFFICIENTLY SYNCHRONIZE MULTIPLE MEASUREMENTS ACROSS MULTIPLE SENSOR INPUTS  
A system for synchronizing multiple measurements across multiple sensors is provided. The system implements an algorithm in combination with highly flexible hardware architecture that generally...
US20140214355 METHOD AND APPARATUS FOR VERIFYING CIRCUIT DESIGN  
A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first...
US20090099828 Device Threshold Calibration Through State Dependent Burnin  
Disclosed are embodiments of a design structure for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g.,...
US20050033542 Debugger apparatus and debugging method  
A debugger apparatus according to the present embodiment comprises a host, CPU, a plurality of E-memory units (emulation memory units) for storing instructions, and an execution supervision unit....
US20070198205 TEST APPARATUS  
A test apparatus that tests a plurality of electronic devices in parallel is provided. The test apparatus includes: a pattern generating section that generates a test pattern provided to the...
US20090006021 METHOD AND APPARATUS FOR IMPLEMENTING SCALED DEVICE TESTS  
A method includes defining a hierarchy of test routines in a test program for testing integrated circuit devices. A first device is tested at a first screening level in the hierarchy. The first...
US20150120234 SMART HANDLER RESOURCE DISTRIBUTION SYSTEM  
A system for concurrently testing multiple semiconductor components includes multiple testers, each including a processor and a memory configured to store and execute control signals for...
US20100114520 TEST APPARATUS, TEST METHOD, PROGRAM, AND RECORDING MEDIUM REDUCING THE INFLUENCE OF VARIATIONS  
Provided is a test apparatus that tests a device under test, including a vector expanding section that sequentially generates a plurality of test vectors; a predicting section that calculates a...
US20150198658 METHOD AND EQUIPMENT FOR TESTING SEMICONDUCTOR APPARATUSES SIMULTANEOUSLY AND CONTINUOUSLY  
A method for testing a plurality of semiconductor apparatuses, the method including mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor...
US20140114603 PSEUDO TESTER-PER-SITE FUNCTIONALITY ON NATIVELY TESTER-PER-PIN AUTOMATIC TEST EQUIPMENT FOR SEMICONDUCTOR TEST  
A system and method for testing devices are presented. Embodiments of the present invention use a central controller to coordinate the testing of a plurality of devices under test as well as a...
US20130197851 TEST CONTROLLER FOR 3D STACKED INTEGRATED CIRCUITS  
Stacked IC devices (or 3D semiconductor devices) have two or more semiconductor devices stacked so they occupy less space than two or more conventionally arranged semiconductor devices. Access to...
US20120253730 DIRECT CURRENT CIRCUIT TESTING DEVICE AND METHOD FOR USING SAME  
A method for testing electronic devices that are correspondingly connected to test units includes generating control signals for the electronic devices that are connected to one or more test units...
US20110184687 TEST APPARATUS AND TEST METHOD  
A test apparatus for testing a device under test includes a test module that exchanges signals with the device under test to test the device under test, a test controller that includes a processor...
US20160266198 METHOD FOR IC TESTING BIGDATA ANALYSIS OPTION VALUE ANALYSIS  
A method for IC testing bigdata analysis and option value analysis includes: dividing a wafer into devices under test to undergo an electrical property test, retrieving data detected of the...
US20150362548 WAFER MAP IDENTIFICATION SYSTEM FOR WAFER TEST DATA  
A wafer map identification system for wafer test data includes a capturing unit configured to collect the test data of each wafer chip from the wafer testing device; an execution interface for...
US20150309111 Multiple Rate Signature Test to Verify Integrated Circuit Identity  
Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester...
US20150185277 VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR  
A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a...

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