Matches 1 - 50 out of 335 1 2 3 4 5 6 7 >


Match Document Document Title
US20150037979 CONFORMAL SIDEWALL PASSIVATION  
A method for etching features into an etch layer in a stack disposed below a patterned mask with mask features is provided. Coating providing molecules are provided. The coating providing...
US20120231630 Etching Gas  
Disclosed is an etching gas provided containing CHF2COF. The etching gas may contain, as an additive, at least one kind of gas selected from O2, O3, CO, CO2, F2, NF3, Cl2, Br2, I2, XFn (In this...
US20110053378 Dielectric Etching  
An etchant for dielectrics, such as silicon dioxide, that leaves monocrystalline silicon surface exposed by the etchant free of etch damage, such as etch pits, when the etch is done in the...
US20150200106 HIGH ASPECT RATIO ETCH WITH COMBINATION MASK  
A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second...
US20050085084 Method of fabricating copper metallization on backside of gallium arsenide devices  
A bi-level structure based on copper metallization technique has been applied to backside of gallium arsenide (GaAs) devices. The foundation where the structure stands on is device substrate...
US20080102642 METHOD OF SEASONING IDLE SILICON NITRIDE ETCHER AND METHOD OF ACTIVATING  
A method of seasoning an idle silicon nitride etcher is described. A buffer material having stronger adhesion to an internal wall of the chamber of the silicon nitride etcher than silicon nitride...
US20120220134 METHOD FOR CLEARING NATIVE OXIDE  
A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the...
US20120135558 METHOD OF ETCHING ASYMMETRIC WAFER, SOLAR CELL INCLUDING THE ASYMMETRICALLY ETCHED WAFER, AND METHOD OF MANUFACTURING THE SAME  
With the present invention, two wafers for a solar cell only whose light receiving surfaces are selectively etched can be simultaneously obtained by overlapping the two wafers and performing a...
US20120021604 Controlling Defects in Thin Wafer Handling  
A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not...
US20120238101 SELECTIVITY IN A XENON DIFLUORIDE ETCH PROCESS  
A method and an apparatus for etching microstructures and the like that provides improved selectivity to surrounding materials when etching silicon using xenon difluoride (XeF2). Etch selectivity...
US20070134927 METHOD FOR REMOVING RESIDUES FORMED DURING THE MANUFACTURE OF MEMS DEVICES  
A method of removing residues from an integrated device, in particular residues resulting from processing in HF vapor, is disclosed wherein the fabricated device is exposed to dry water vapor for...
US20050221618 System for controlling a plenum output flow geometry  
A flow control system disrupts a reactive flow into a process chamber in order to shape the flow geometry issuing into a substrate processing chamber. In one embodiment, gas is injected into a...
US20080050923 Low-k damage avoidance during bevel etch processing  
A method for etching a bevel edge of a substrate is provided. A patterned photoresist mask is formed over the etch layer. The bevel edge is cleaned comprising providing a cleaning gas comprising...
US20110183520 Method for Removing Copper Oxide Layer  
The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper...
US20140353774 METHODS FOR STICTION REDUCTION IN MEMS SENSORS  
A method of the invention includes reducing stiction of a MEMS device by providing a conductive path for electric charge collected on a bump stop formed on a substrate. The bump stop is formed by...
US20140113452 WAFER EDGE TRIMMING METHOD  
A wafer edge trimming method comprises steps as follows: Firstly, an etch-resistant layer is formed on a surface of a wafer. A wet treatment process is then performed to remove a portion of the...
US20090170332 PROCESSING GAS SUPPLYING SYSTEM AND PROCESSING GAS SUPPLYING METHOD  
A gas supplying system includes a processing gas supply pipe for supplying a processing gas from a gas cylinder 210 into a processing apparatus and a nonreactive gas supply source 230 for...
US20120094498 METHOD FOR REDUCING PUNCH-THROUGH DEFECTS  
A method for reducing punch-through defects during semiconductor fabrication is disclosed. Various parameters such as partial pressure, total pressure, and temperature are manipulated to reduce...
US20060042755 Large surface area dry etcher  
A dry etcher includes a process chamber configured to process a substrate therein using plasma; a substrate supporter to support the substrate; an inner chamber wall maintained at a high...
US20060060847 Silicon-insulator-silicon structure and method for fabricating the same  
A silicon-insulator-silicon structure with an insulator having a plurality of openings and a method for fabricating the same are provided. The silicon-insulator-silicon structure includes a lower...
US20150069622 Via Definition Scheme  
A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second...
US20140193965 REDUCTION OF BASAL PLANE DISLOCATIONS IN EPITAXIAL SiC USING AN IN-SITU ETCH PROCESS  
A method of: providing an off-axis 4H—SiC substrate, and etching the surface of the substrate with hydrogen or an inert gas.
US20050272265 Dual damascene integration structure and method for forming improved dual damascene integration structure  
Methods for forming a dual damascene dielectric structure in a porous ultra-low-k (ULK) dielectric material by using gas-cluster ion-beam processing are disclosed. These methods minimize hard-mask...
US20090085169 METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS  
A high aspect ratio silicon structure comprises a silicon substrate (110) having a surface (111), an electrically insulating layer (120) over portions of the silicon substrate, a hardmask (130)...
US20050054205 Mask trimming apparatus and mask trimming method  
A plasma etching apparatus and method are provided to obtain an accurate dimension after trimming based on an amount of roughness of a mask edge or an amount of radicals in plasma. A wafer on the...
US20120070995 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a...
US20060043066 Processes for pre-tapering silicon or silicon-germanium prior to etching shallow trenches  
A process for pre-tapering features in a material, such as silicon, prior to etching shallow trenches in the material includes opening a hard mask over the material such that first pre-tapered...
US20150031212 METHOD FOR OBTAINING EXTREME SELECTIVITY OF METAL NITRIDES AND METAL OXIDES  
Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The...
US20130223790 Optical Waveguide Arrangements Comprising An Auxiliary Waveguide - Like Structure  
An optical waveguide arrangement is provided which comprises an active ridge waveguide structure 12 formed by etching of a semiconductor substrate 1, 2, 3. There is also provided an auxiliary...
US20140190399 REDUCTION OF BASAL PLANE DISLOCATIONS IN EPITAXIAL SiC USING AN IN-SITU ETCH PROCESS  
A method of: providing an off-axis silicon carbide substrate, and etching the surface of the substrate with a dry gas, hydrogen, or an inert gas.
US20090093123 Spin head, chuck pin used in the spin head, and method for treating a substrate with the spin head  
Provided is a spin head for supporting a substrate. The spin head includes a rotatable body, and chuck pins protruding upward from the body and configured to support an edge of a substrate placed...
US20070056930 POLYSILICON ETCHING METHODS  
Polysilicon etching methods are disclosed that employ a gas flow including perfluorocyclopentene (C5F8) and nitrogen trifluoride (NF3). The etching methods achieved a substantially vertical...
US20060216940 Methods of producing structures for electron beam induced resonance using plating and/or etching  
We describe an ultra-small structure and a method of producing the same. The structures produce visible light of varying frequency, from a single metallic layer. In one example, a row of metallic...
US20110151670 METHOD OF CONTROLLING ETCH MICROLOADING FOR A TUNGSTEN-CONTAINING LAYER  
A method for etching features of different aspect ratios in a tungsten containing layer is provided. An etch gas is provided containing a tungsten etch component and a deposition component. A...
US20050266691 Carbon-doped-Si oxide etch using H2 additive in fluorocarbon etch chemistry  
Certain embodiments include an etching method including providing an etch material, applying a gas mixture including hydrogen, forming a plasma, and etching the etch material. The etch material...
US20070287296 Dry etching method for oxide semiconductor film  
Provided is a dry etching method for an oxide semiconductor film made of In—Ga—Zn—O, in which an etching gas containing a hydrocarbon is used in a dry etching process for the oxide semiconductor...
US20150024600 SYSTEMS AND METHODS TO MITIGATE NITRIDE PRECIPITATES  
A method of fabricating a semiconductor device is disclosed. A substrate having an oxide layer is provided. At least a portion of the oxide layer is removed and forms a nitride layer. The nitride...
US20090233449 ETCHING CHAMBER WITH SUBCHAMBER  
In an apparatus for etching a semiconductor wafer or sample (101), the semiconductor wafer or sample is placed on a sample holder (104) disposed in a first chamber (103). The combination of the...
US20070181529 Corona discharge plasma source devices, and various systems and methods of using same  
The present invention is generally directed to corona discharge plasma source devices, and various systems and methods for using same. In one illustrative embodiment, the system comprises a...
US20070298607 Method for copper damascence fill for forming an interconnect  
Methods of fabricating an interconnect, which fundamentally comprises etching back on an overhang section formed over a portion of an opening formed in a dielectric layer, said etching back is...
US20110177693 Reversible Water-Free Process for the Separation of Acid-Containing Gas Mixtures  
Gas mixtures which comprise acids like HF, HCl or HBr and other constituents, especially gas mixtures which comprise or consist of carboxylic acid fluorides, C(O)F2 or phosphorous pentafluoride...
US20070026682 Method for advanced time-multiplexed etching  
A method of anisotropic plasma etching of a substrate material through a window defined in an etching mask comprises the steps of: disposing a hard mask material by injection of a precursor gas or...
US20050145892 Mask, semiconductor device manufacturing method, and semiconductor device  
A mask capable of improving superimposing accuracy of patterns drawn on a plurality of masks, a production method of a semiconductor device capable of improving a yield of semiconductor devices,...
US20080254636 Etching of silicon oxide film  
An etching method includes preparing a target object such that a first oxide film made of silicon oxide containing at least one of B and P is formed on a substrate, a second oxide film made of...
US20140187049 SHOWERHEAD ELECTRODE ASSEMBLY WITH GAS FLOW MODIFICATION FOR EXTENDED ELECTRODE LIFE  
A showerhead electrode assembly for a plasma processing apparatus is provided. The showerhead electrode assembly includes a first member attached to a second member. The first and second members...
US20070238301 Batch processing system and method for performing chemical oxide removal  
A batch processing system and method for chemical oxide removal (COR) is described. The batch processing system is configured to provide chemical treatment of a plurality of substrates, wherein...
US20070093069 PURGE PROCESS AFTER DRY ETCHING  
A purge process for a chip performed after a dry etching process is provided. The dry etching process is carried out inside a reaction chamber. The purge process is used to remove any byproducts...
US20050236366 Use of C2F6 gas to gain vertical profile in high dosage implanted poly film  
A method of etching a polysilicon layer comprising the following steps. A polysilicon layer is formed over a structure and the polysilicon layer is etched using at least a C2F6 etching process to...
US20060148263 Dry etching apparatus having particle removing device and method of fabricating phase shift mask using the same  
A dry etching apparatus may include a dry etching chamber and a door chamber. The apparatus may further include a load lock chamber configured to connect the dry etching chamber and the door...
US20100055917 METHOD FOR FORMING ACTIVE PILLAR OF VERTICAL CHANNEL TRANSISTOR  
A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch...

Matches 1 - 50 out of 335 1 2 3 4 5 6 7 >