|
Match
|
Document |
Document Title |
|
|
US20130267095 |
METHOD OF FABRICATING AND CORRECTING NANOIMPRINT LITHOGRAPHY TEMPLATES
A method of fabricating a nanoimprint lithography template includes installing a reticle on a reticle stage of scanning lithography equipment having a light source, the reticle stage and a... |
|
|
US20150076663 |
Patterned Bases, and Patterning Methods
Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing... |
|
|
US20140091434 |
Patterned Bases, and Patterning Methods
Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing... |
|
|
US20120282764 |
TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS
In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a... |
|
|
US20120184106 |
METHOD AND ALGORITHM FOR RANDOM HALF PITCHED INTERCONNECT LAYOUT WITH CONSTANT SPACING
An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having... |
|
|
US20090047790 |
Selective Wet Etching of Hafnium Aluminum Oxide Films
Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlOx) material relative to silicon oxide (SiOx) are provided. |
|
|
US20140377885 |
PROCESS FLOW FOR REPLACEMENT METAL GATE TRANSISTORS
A replacement metal gate transistor and methods of forming replacement metal gate transistors are described. Various examples provide methods of manufacturing a replacement metal gate transistor... |
|
|
US20150200109 |
MASK PASSIVATION USING PLASMA
A gas comprising hydrogen is supplied to a plasma source. Plasma comprising hydrogen plasma particles is generated from the gas. A passivation layer is deposited on a first mask layer on a second... |
|
|
US20150111387 |
USE OF TOPOGRAPHY TO DIRECT ASSEMBLY OF BLOCK COPOLYMERS IN GRAPHO-EPITAXIAL APPLICATIONS
A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed... |
|
|
US20140017899 |
DOUBLE PATTERNING LITHOGRAPHY TECHNIQUES
Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning... |
|
|
US20150171029 |
INVERSE NANOSTRUCTURE DIELECTRIC LAYERS
Embodiments of the present disclosure describe dielectric layers and methods for their fabrication and use. In some embodiments, a dielectric layer may include a dielectric material and a... |
|
|
US20120295445 |
Methods of Fabricating Substrates
A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced... |
|
|
US20150064917 |
UV-Assisted Stripping of Hardened Photoresist to Create Chemical Templates for Directed Self-Assembly
A processing method is disclosed that enables an improved directed self-assembly (DSA) processing scheme by allowing the formation of improved guide strips in the DSA template that may enable the... |
|
|
US20080299776 |
FREQUENCY DOUBLING USING SPACER MASK
A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of... |
|
|
US20150087154 |
HIGH ASPECT RATIO ETCH WITH COMBINATION MASK
A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second... |
|
|
US20150187579 |
STRESS-CONTROLLED FORMATION OF TiN HARD MASK
A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress... |
|
|
US20150170905 |
METHODS FOR DEVICE FABRICATION USING PITCH REDUCTION AND RELATED DEVICES
Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied... |
|
|
US20140093218 |
SILICON-BASED OPTICAL FIBER CLAMP AND METHODS OF FABRICATING THE SAME
An optical fiber clamp and fabrication method thereof are disclosed. The optical fiber clamp includes one or more clamp units. Each clamp unit includes a clamp body formed of silicon, a guide hole... |
|
|
US20140008806 |
STAIR STEP FORMATION USING AT LEAST TWO MASKS
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material... |
|
|
US20100297848 |
ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE
The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch... |
|
|
US20120187467 |
FLOATING GATES AND METHODS OF FORMATION
The present invention generally relates to a floating gate structure and method of forming the same. The floating gate structure has an upper portion which is wider than a middle portion of the... |
|
|
US20110124197 |
METHOD TO IMPROVE THE RELIABILITY OF THE BREAKDOWN VOLTAGE IN HIGH VOLTAGE DEVICES
A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device. |
|
|
US20100311244 |
DOUBLE-EXPOSURE METHOD
The present invention discloses a double-exposure method comprising a first lithography process and a second lithography process. Between the first and the second lithography process, coat... |
|
|
US20130244439 |
REMOVABLE TEMPLATES FOR DIRECTED SELF ASSEMBLY
A sacrificial-post templating method is presented for directing block copolymer (BCP) self-assembly to form nanostructures of monolayers and bilayers of microdomains. The topographical post... |
|
|
US20140329389 |
BULK NANO-RIBBON AND/OR NANO-POROUS STRUCTURES FOR THERMOELECTRIC DEVICES AND METHODS FOR MAKING THE SAME
Structure including nano-ribbons and method thereof. The structure include multiple nano-ribbons. Each of the multiple nano-ribbons corresponds to a first end and a second end, and the first end... |
|
|
US20130187130 |
BULK NANO-RIBBON AND/OR NANO-POROUS STRUCTURES FOR THERMOELECTRIC DEVICES AND METHODS FOR MAKING THE SAME
Structure including nano-ribbons and method thereof. The structure include multiple nano-ribbons. Each of the multiple nano-ribbons corresponds to a first end and a second end, and the first end... |
|
|
US20130183829 |
METHODS FOR INCREASED ARRAY FEATURE DENSITY
A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers... |
|
|
US20140210004 |
SELF-ADJUSTING GATE HARD MASK
A method provides an intermediate semiconductor device structure and includes providing a water having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non... |
|
|
US20150155171 |
Lithography Using High Selectivity Spacers for Pitch Reduction
A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over... |
|
|
US20110201207 |
BACKPLANE STRUCTURES FOR SOLUTION PROCESSED ELECTRONIC DEVICES
There is provided a backplane for an organic electronic device. The backplane has a TFT substrate; a multiplicity of electrode structures; and a bank structure defining a multiplicity of pixel... |
|
|
US20120064725 |
NAPHTHALENE DERIVATIVE, RESIST BOTTOM LAYER MATERIAL, AND PATTERNING PROCESS
A naphthalene derivative having formula (1) is provided wherein An and Art denote a benzene or naphthalene ring, and n is such a natural number as to provide a weight average molecular weight of... |
|
|
US20090289309 |
METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and... |
|
|
US20140374856 |
Apparatus and Method for Preventing Stiction of MEMS Devices Encapsulated by Active Circuitry
One or more stopper features (e.g., bump structures) are formed in a standard ASIC wafer top passivation layer for preventing MEMS device stiction vertically in integrated devices having a MEMS... |
|
|
US20150111386 |
USE OF TOPOGRAPHY TO DIRECT ASSEMBLY OF BLOCK COPOLYMERS IN GRAPHO-EPITAXIAL APPLICATIONS
A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed... |
|
|
US20120322269 |
Methods of Fabricating Substrates
A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in... |
|
|
US20110159695 |
METHOD FOR MANUFACTURING MASK
Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger... |
|
|
US20120092771 |
EMBEDDED VERTICAL OPTICAL GRATING FOR HETEROGENEOUS INTEGRATION
An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating... |
|
|
US20130115724 |
METHOD OF FABRICATING AN INTEGRATED ORIFICE PLATE AND CAP STRUCTURE
In an embodiment, a method of fabricating an integrated orifice plate and cap structure includes forming an orifice bore on the front side of a product wafer, coating side walls of the orifice... |
|
|
US20140315389 |
CRACK CONTROL FOR SUBSTRATE SEPARATION
A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by... |
|
|
US20130260563 |
Mask Treatment for Double Patterning Design
A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or... |
|
|
US20110186910 |
METHODS OF PREPARING FLEXIBLE PHOTOVOLTAIC DEVICES USING EPITAXIAL LIFTOFF, AND PRESERVING THE INTEGRITY OF GROWTH SUBSTRATES USED IN EPITAXIAL GROWTH
There is disclosed methods of making photosensitive devices, such as flexible photovoltaic (PV) devices, through the use of epitaxial liftoff. Also described herein are methods of preparing... |
|
|
US20090017631 |
SELF-ALIGNED PILLAR PATTERNING USING MULTIPLE SPACER MASKS
A method for fabricating a semiconductor mask is described. The image of a series of lines from a first spacer mask is first provided to a mask layer to form a patterned mask layer. The image of a... |
|
|
US20110244690 |
COMBINATORIAL PLASMA ENHANCED DEPOSITION AND ETCH TECHNIQUES
According to various embodiments of the disclosure, an apparatus and method for enhanced deposition and etch techniques is described, including a pedestal, the pedestal having at least two... |
|
|
US20090269918 |
METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SMOOT SIDEWALLS AND ROUNDED TOP CORNERS AND EDGES
Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A... |
|
|
US20090291560 |
FORMING METHOD OF ETCHING MASK, CONTROL PROGRAM AND PROGRAM STORAGE MEDIUM
A feedforward control is performed so that a line width of a mask constituted by an Si3N4 layer 102 formed by using a photoresist 105b as a mask is to be the same as a line width of a mask pattern... |
|
|
US20090286404 |
Method of forming minute patterns in semiconductor device using double patterning
A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between... |
|
|
US20150050811 |
CRITICAL DIMENSION AND PATTERN RECOGNITION STRUCTURES FOR DEVICES MANUFACTURED USING DOUBLE PATTERNING TECHNIQUES
An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features... |
|
|
US20130207108 |
Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques
An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features... |
|
|
US20140256142 |
METHOD OF ETCHING AN ETCH LAYER
A method for etching an etch layer is provided. A glue layer having metallizable terminations is formed over the etch layer. The glue layer is exposed to a patterned light, wherein the... |
|
|
US20090267175 |
DOUBLE PATTERNING TECHNIQUES AND STRUCTURES
Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated... |