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US20110018134 Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride  
By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless...
US20100320609 WETTING PRETREATMENT FOR ENHANCED DAMASCENE METAL FILLING  
Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed...
US20140264874 Electro-Migration Barrier for Cu Interconnect  
Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer...
US20050159004 System for reducing corrosion effects of metallic semiconductor structures  
The present invention defines a system for impeding corrosive egress from a metallic trench structure (206) during the production of a semiconductor device segment (200). The system of the present...
US20130299985 PROCESS FOR FABRICATING GALLIUM ARSENIDE DEVICES WITH COPPER CONTACT LAYER  
Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a...
US20110254164 SELF-ALIGNED BARRIER LAYERS FOR INTERCONNECTS  
An interconnect structure for integrated circuits incorporates manganese silicate and manganese silicon nitride layers that completely surrounds copper wires in integrated circuits and methods for...
US20130147047 Integrated Circuit and Method of Forming an Integrated Circuit  
An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of...
US20050127516 Small viatops for thick copper connectors  
The present invention relates to integrated circuits comprising a protective overcoat and thick copper connectors. According to one aspect of the inventions, vias in the protective overcoat are...
US20080026579 COPPER DAMASCENE PROCESS  
A copper damascene process includes providing a substrate having a dielectric layer thereon, forming at least a copper damascene structure in the dielectric layer, performing a heat treatment on...
US20070298602 Method for Applying Solder to Redistribution Lines  
In a method of making an electronic component, an electrically conductive redistribution line is formed on a surface of a semiconductor chip. The redistribution line includes a solder pad. A...
US20060163731 Dual damascene interconnections employing a copper alloy at the copper/barrier interface  
A method of fabricating a dual damascene interconnection is provided. The method begins by forming on a substrate a dielectric layer and forming a via in the dielectric layer. The dielectric layer...
US20100248472 Methods Of Forming Copper-Comprising Conductive Lines In The Fabrication Of Integrated Circuitry  
A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line trenches are formed into the...
US20060189127 Method to improve palanarity of electroplated copper  
Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by...
US20080122103 EMBEDDED NANO UV BLOCKING BARRIER FOR IMPROVED RELIABILITY OF COPPER/ULTRA LOW K INTERLEVEL DIELECTRIC ELECTRONIC DEVICES  
An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of...
US20070035025 Damascene processing using dielectric barrier films  
Damascene processing is implemented with dielectric barrier films for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films to avoid...
US20070132082 Copper plating connection for multi-die stack in substrate package  
An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another...
US20100065967 Copper interconnection, method for forming copper interconnection structure, and semiconductor device  
A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a...
US20060118422 Electro chemical plating addictives for improving stress and leveling effect  
A chemical solution for an electro chemical plating process includes an electro chemical plating solution; and an additive, added in the electro chemical plating solution, substantially consisting...
US20100079246 INTEGRATED CIRCUIT WITH A RECTIFIER ELEMENT  
An integrated circuit with a rectifier element. One embodiment provides a signal source, an electronic circuit and a rectifier element with a copper layer and a cuprous oxide layer adjacent to and...
US20060035457 Interconnection capacitance reduction  
An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the...
US20050037613 Diffusion barrier for copper lines in integrated circuits  
A method for forming improved diffusion barriers for copper lines in integrated circuits is described. A low-k dielectric layer (10) is formed over a semiconductor (5). A trench (15) is formed in...
US20050020061 Method of modifying conductive wiring  
A method of modifying a conductive wiring. First, a semiconductor substrate is provided. Next, a first barrier is formed on the semiconductor. A conductive wiring is formed on the first barrier. A...
US20050282300 Back-end-of-line metallization inspection and metrology microscopy system and method using x-ray fluorescence  
Systems and methods for performing inspection and metrology operations on metallization processes such as on back-end-of-line (BEOL) metallization thickness and step coverage are disclosed....
US20120326316 METAL CONTACTS FOR MOLECULAR DEVICE JUNCTIONS AND SURFACE-DIFFUSION-MEDIATED DEPOSITION  
Metal contact formation for molecular device junctions by surface-diffusion-mediated deposition (SDMD) is described. In an example, a method of fabricating a molecular device junction by...
US20080318424 Photoresist residue remover composition and semiconductor circuit element production process employing the same  
A photoresist residue remover composition is provided that removes a photoresist residue formed by a resist ashing treatment after dry etching in a step of forming, on a substrate surface, wiring...
US20060138670 Method of forming copper line in semiconductor device  
A method of forming a copper line in a semiconductor device may enhance reliability of the copper line. The method includes the steps of forming a trench in a substrate; forming a copper layer...
US20090176369 LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES  
A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier,...
US20060286797 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects  
Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain...
US20120040531 METHOD TO FABRICATE THIN METAL VIA INTERCONNECTS ON COPPER WIRES IN MRAM DEVICES  
A scheme for forming a thin metal interconnect is disclosed that minimizes etch residues and provides a wet clean treatment for via openings. A single layer interlayer dielectric (ILD), BARC, and...
US20060267201 Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layer  
By providing a stiffening layer at three sidewalls of a trench to be filled with a copper-containing metal, the reduced thermomechanical confinement of a low-k material may be compensated for, at...
US20070093058 METHOD FOR PRODUCING ELECTRIC CONTACT AND ELECTRICAL CONNECTOR  
A method for producing an electric contact extending from a copper foil, comprises steps of fixing a cover lay having a hole of a diameter smaller than that of the copper foil of a predetermined...
US20080045013 Iridium encased metal interconnects for integrated circuit applications  
An iridium encased copper interconnect comprises an iridium liner formed within a trench in a dielectric layer, wherein the iridium liner is formed directly on the dielectric layer, a copper...
US20060046481 Manufacturing methods and electroless plating apparatus for manufacturing wiring circuit boards  
A manufacturing method for wiring circuit boards enhances product yield and promotes uniform electrical characteristics among the products by reducing fluctuations in the thickness of the...
US20070096221 SEMICONDUCTOR DEVICE COMPRISING COPPER-BASED CONTACT PLUG AND A METHOD OF FORMING THE SAME  
By providing a tungsten nitride barrier layer for a contact plug, well-approved copper-based via formation techniques may be used to form a highly conductive contact plug, thereby significantly...
US20100136789 Dielectric Barrier Deposition Using Oxygen Containing Precursor  
A method is provided for depositing a dielectric barrier film including a precursor with silicon, carbon, oxygen, and hydrogen with improved barrier dielectric properties including lower...
US20080108193 Cu annealing for improved data retention in flash memory devices  
Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu....
US20090039515 IONIZING RADIATION BLOCKING IN IC CHIP TO REDUCE SOFT ERRORS  
Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip;...
US20070072420 Method of forming copper interconnection using dual damascene process and semiconductor device having copper interconnection according to the same  
Disclosed is a method of forming a copper interconnection using a dual damascene process, in which an etch profile anomaly and the trench depth variation caused by the trench etching process are...
US20060001170 Conductive compound cap layer  
An interconnect structure and method thereof comprising: a interconnect and a compound cap layer. The interconnect has a compound cap layer thereover. The interconnect is preferably comprised of...
US20060024901 Method for fabricating a high-frequency and high-power semiconductor module  
A method for fabricating a high-frequency and high-power semiconductor module uses two stages respectively adopting a thick-film process to form resistors or elements of high impedance, and a thin...
US20070259523 Method of fabricating high speed integrated circuits  
This invention describes a new method of fabricating high speed chips such as microprocessors used in servers. The biggest problem limiting the speed of these chips is the heat generated by such a...
US20070202699 Electronic component fabrication method  
A method for fabricating an electronic component, includes forming a seed film above a base body, cooling said seed film, and putting the cooled seed film into a plating solution to perform...
US20070190783 Patterning crystalline compounds on surfaces  
A method of patterning the surface of a substrate with at least one organic semiconducting compound, comprising the steps of: (a) providing a stamp having a surface including a plurality of...
US20080227294 Method of making an interconnect structure  
A method of making an interconnect structure includes providing a die (120) having an electrically conducting pad (140) and further includes using electrophoresis to place a plurality of...
US20070072415 Method for integrating a ruthenium layer with bulk copper in copper metallization  
A method for integrating a Ru layer with bulk Cu in semiconductor manufacturing. The method includes depositing a Ru layer onto a substrate in a chemical vapor deposition process, modifying the...
US20070281476 Methods for forming thin copper films and structures formed thereby  
Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a thin conformal copper layer on a surface by utilizing a formation...
US20050136638 Low temperature sintering nanoparticle compositions  
A composition contains a mixture of silver and gold metallic nanoparticles. The composition can be deposited on a substrate and sintered to form a conductive element.
US20070004210 Polishing composition and polishing method  
To provide a polishing composition which has a high removal rate and enables to suppress occurrence of dishing and erosion, in polishing of a surface to be polished in the production of a...
US20060183257 Method for analyzing electrolytic copper plating solution, and analyzing device therefor and production method for semi-conductor product  
Effective fillability and the uniformity electrodeposition of a copper electroplating solution is judged by determining the time-dependent potential change thereof at a cathode current density of...
US20070128872 Polishing composition and polishing method  
As a polishing composition which allows high-speed polishing while dishing and erosion are prevented and the flatness of metal film is maintained, there is provided a polishing composition for...
Matches 1 - 50 out of 161 1 2 3 4 >