Matches 1 - 50 out of 324 1 2 3 4 5 6 7 >


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US20110140278 OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION  
An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation...
US20150115414 SAPPHIRE STRUCTURE WITH METAL SUBSTRUCTURE AND METHOD FOR PRODUCING THE SAME  
A sapphire structure with a metal substructure is disclosed. The sapphire structure with a metal substructure includes a sapphire structure and a metal substructure. The sapphire structure...
US20140239505 Bump-on-Trace Methods and Structures in Packaging  
A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder...
US20110124193 CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION  
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning...
US20150076624 INTEGRATED CIRCUITS HAVING SMOOTH METAL GATES AND METHODS FOR FABRICATING SAME  
Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit...
US20110309717 TWO-DIMENSIONAL COMB-DRIVE ACTUATOR AND MANUFACTURING METHOD THEREOF  
A two-dimensional comb-drive actuator and manufacturing method thereof are described. The two-dimensional comb-drive actuator includes a supporting base, a frame and a movable body. The supporting...
US20080003818 NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING  
By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved...
US20150140812 METHODS FOR DRY ETCHING COBALT METAL USING FLUORINE RADICALS  
Embodiments of methods for etching cobalt metal using fluorine radicals are provided herein. In some embodiments, a method of etching a cobalt layer in a substrate processing chamber includes:...
US20100015752 Methods of Preparing Photovoltaic Modules  
Methods of preparing photovoltaic modules, as well as related components, systems, and devices, are disclosed.
US20070212878 VARIABLE WIDTH CONDUCTIVE LINES HAVING SUBSTANTIALLY CONSTANT IMPEDANCE  
A method of fabricating a conductive line provides a substrate having a blanket layer of conductive material disposed thereon, a removing of a first portion of the blanket layer of conductive...
US20130100185 ALCu HARD MASK PROCESS  
A process for forming a metal interconnection in an integrated circuit includes forming a first metal layer and a second metal layer on the first metal layer. Photoresist is placed on the second...
US20100041232 Adjustable dummy fill  
A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is...
US20120149169 METHOD FOR MANUFACTURING MASK  
Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger...
US20120204950 TRANSPARENT CONDUCTIVE COATINGS FOR OPTOELECTRONIC AND ELECTRONIC DEVICES  
The invention provides processes for the manufacture of conductive transparent films and electronic or optoelectronic devices comprising same.
US20140349481 Air-Gap Formation in Interconnect Structures  
A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the...
US20070072421 Method to passivate defects in integrated circuits  
Defects in an integrated circuit are electrically passivated. A hydrogen diffusion blocking film is placed on the integrated circuit. Atomic hydrogen is implanted through the hydrogen diffusion...
US20100075497 Non-Plating Line Plating Method Using Current Transmitted From Ball Side  
A non-plating line (NPL) plating method is provided. The NPL plating method is featured in that at first it forms a circuit layer on a bump side only, and therefore a plating current can be...
US20090061625 LCD DRIVER IC AND METHOD FOR MANUFACTURING THE SAME  
An LCD driver IC and a method for manufacturing the same. In one example embodiment, an LCD driver IC includes first and second main poly patterns formed separately from each other, a connection...
US20130115770 ETCHING COMPOSITION, METHOD OF FORMING A METAL PATTERN AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE  
An etching composition for a copper-containing layer includes about 0.1% to about 30% by weight of ammonium persulfate, about 0.1% to about 10% by weight of a sulfate, about 0.01% to about 5% by...
US20140167257 FABRICATION OF THREE-DIMENSIONAL HIGH SURFACE AREA ELECTRODES  
A method for fabricating three dimensional high surface electrodes is described. The methods including the steps: designing the pillars; selecting a material for the formation of the pillars;...
US20130095599 PHOTOVOLTAIC DEVICE USING NANO-SPHERES FOR TEXTURED ELECTRODES  
An electronic device includes a substrate and a plurality of particles anchored to the substrate. An electrode material is formed over the particles and configured to form peaks over the...
US20100055900 MASK AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME  
A mask for forming a metal line and a via contact, and a method for fabricating a semiconductor device using the same, minimizes misalignment. The mask includes a first mask region having a dark...
US20110068436 METHODS AND STRUCTURES FOR ENHANCING PERIMETER-TO-SURFACE AREA HOMOGENEITY  
Methods and structures for enhancing the homogeneity in a ratio of perimeter to surface area among heterogeneous features in different substrate regions. At least one shape on the substrate...
US20090200548 GUARD RING EXTENSION TO PREVENT REALIABILITY FAILURES  
An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal...
US20130234303 METAL SHIELD FOR INTEGRATED CIRCUITS  
A metal shield structure is provided for an integrated circuit (IC) having at least a first metal contact coupled to a fixed potential and a second metal contact. A first passivation layer is...
US20100001403 Method for designing semiconductor integrated circuit which includes metallic wiring connected to gate electrode and satisfies antenna criterion  
A method of designing a semiconductor integrated circuit, includes verifying an antenna ratio of a metallic wiring connected to a first gate electrode and the first gate electrode, based on a...
US20110008962 METHOD FOR FABRICATING A MULTILAYER MICROSTRUCTURE WITH BALANCING RESIDUAL STRESS CAPABILITY  
A method for fabricating a multilayer microstructure with balancing residual stress capability includes forming a multilayer microstructure on a substrate and conducting a step of isotropic plasma...
US20140077380 BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES  
An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground...
US20090305456 Method of Manufacturing Back Junction Solar Cell  
A method of manufacturing a back junction solar cell comprises the steps of forming a first diffusion mask (9) on the back of a silicon substrate (1), printing a first etching paste (3a, 4a) on a...
US20150187590 Methods for Uniform Imprint Pattern Transfer of Sub-20 nm Features  
Methods of increasing etch selectivity in imprint lithography are described which employ material deposition techniques that impart a unique morphology to the multi-layer material stacks, thereby...
US20140284188 MEMS DEVICE AND METHOD OF MANUFACTURING THE SAME  
According to one embodiment, a MEMS device comprises a first electrode provided on a support substrate, a second electrode opposed to the first electrode and movable in the direction it is opposed...
US20080277804 Mask Layout Method, and Semiconductor Device and Method for Fabricating the Same  
Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy...
US20100112811 METHOD FOR PATTERNING A METAL GATE  
The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each...
US20100284115 ESD Protection Utilizing Radiated Thermal Relief  
An ESD device with a protection structure utilizing radiated heat dissipation to prevent or reduce thermal failures. The device includes a voltage switchable polymer 10 between electrodes 11 and...
US20050255696 Method of processing resist, semiconductor device, and method of producing the same  
A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4)...
US20090224373 Integrated circuit and method for manufacturing same  
When an integrated circuit having an interlayer insulation film built up on top of a wiring layer is subjected to a heat treatment, it is unlikely that a void formed in the interlayer insulation...
US20140027917 NON-LITHOGRAPHIC LINE PATTERN FORMATION  
A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation...
US20150008788 LOW TEMPERATURE CERAMIC MICROELECTROMECHANICAL STRUCTURES  
A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method providing for processes and manufacturing sequences...
US20150050807 TUNGSTEN DEPOSITION WITH TUNGSTEN HEXAFLUORIDE (WF6) ETCHBACK  
Implementations described herein generally relate to methods for forming tungsten materials on substrates using vapor deposition processes. The method comprises positioning a substrate having a...
US20130221355 STRUCTURES AND METHODS FOR TESTING PRINTABLE INTEGRATED CIRCUITS  
A substrate includes an anchor area (30) physically secured to a surface of the substrate (10) and at least one printable electronic component (20). The at least one printable electronic component...
US20100258785 Superlattice nanopatterning of wires and complex patterns  
Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the...
US20120009785 Depositing Tungsten Into High Aspect Ratio Features  
Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials are provided. The method involves providing a partially fabricated semiconductor substrate and...
US20140113449 Nanoelectromechanical Logic Devices  
Nanoelectromechanical logic devices can include a plurality of flexible bridges having control and logic electrodes. Voltages applied to control electrodes can be used to control flexing of the...
US20140021982 NANOELECTROMECHANICAL LOGIC DEVICES  
Nanoelectromechanical logic devices can include a plurality of flexible bridges having control and logic electrodes. Voltages applied to control electrodes can be used to control flexing of the...
US20100144140 METHODS FOR DEPOSITING TUNGSTEN FILMS HAVING LOW RESISTIVITY FOR GAPFILL APPLICATIONS  
Methods of filling gaps or recessed features on substrates are provided. According to various embodiments, the methods involve bulk deposition of tungsten to partially fill the feature followed by...
US20060086056 Aqueous slurry composition for chemical mechanical planarization  
An aqueous slurry composition of the present invention, comprising a first polyacrylic acid and a second polyacrylic acid having specific weight average molecular weights ranging from 1,000,000 to...
US20130029481 TEMPLATED CIRCUITRY FABRICATION  
A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels...
US20080280409 Memory Arrays, Semiconductor Constructions And Electronic Systems; And Methods Of Forming Memory Arrays, Semiconductor Constructions And Electronic Systems  
Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some...
US20110147935 METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS  
A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to...
US20090050903 Selective wet etching of gold-tin based solder  
The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform...

Matches 1 - 50 out of 324 1 2 3 4 5 6 7 >