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US20120264294 SRAM CELL WITH T-SHAPED CONTACT  
An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater...
US20120264293 SRAM CELL WITH T-SHAPED CONTACT  
An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater...
US20120258593 SRAM CELL WITH T-SHAPED CONTACT  
An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater...
US20110159684 SRAM CELL WITH T-SHAPED CONTACT  
An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater...
US20100308419 SRAM Cell with T-Shaped Contact  
An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater...
US20130043556 SIZE-FILTERED MULTIMETAL STRUCTURES  
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A...
US20150221682 Circuit-on-Wire  
A circuit-on-wire (CoW) is provided that is made from a flexible metal wire with an outer surface, and a plurality of discrete electrical control devices formed in series along the metal wire...
US20120261830 MEMS DEVICE ETCH STOP  
The present disclosure provides a micro-electro-mechanical systems (MEMS) device and a method for fabricating such a device. In an embodiment, a MEMS device includes a substrate, a dielectric...
US20140332965 High Performance Refractory Metal / Copper Interconnects To Eliminate Electromigration  
An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect...
US20150255405 CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP  
A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the...
US20140091466 PITCH QUARTERING TO CREATE PITCH HALVED TRENCHES AND PITCH HALVED AIR GAPS  
A silicon structure is fabricated determining a pattern for wire trenches and air gaps. The wire trenches are created, and certain trenches are used as air gaps. The remaining wire trenches are...
US20110285015 BUMP STRUCTURE AND FABRICATION METHOD THEREOF  
There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top...
US20080124547 PARTIALLY INSULATION COATED METAL WIRE FOR WIRE BONDING AND WIRE BONDING METHOD FOR SEMICONDUCTOR PACKAGE USING THE SAME  
An insulation coated metal wire for wire bonding is provided. The insulation coated metal wire comprises a metal wire; and an insulating layer partially coated on the surface of the metal wire to...
US20110256713 POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS AND IMPRINT PROCESS USING POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS  
A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane...
US20150179591 Backside Redistribution Layer (RDL) Structure  
An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding compound, the passivation layer...
US20150147881 PASSIVATION ASH/OXIDATION OF BARE COPPER  
A semiconductor wafer has a clean, high quality Cu oxide formed at the surface of exposed Cu when an extended non-fabrication process time (such as shipping to an assembly/test site or prolonged...
US20130334698 MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONIC ELEMENTS THEREIN  
A microelectronic assembly tolerant to misplacement of microelectronic elements therein may include a molded structure containing a plurality of microelectronic elements. Each microelectronic...
US20150206872 METHOD OF FORMING CONTACT STRUCTURE OF GATE STRUCTURE  
A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate...
US20150056803 TUNGSTEN FEATURE FILL  
Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features....
US20130302980 TUNGSTEN FEATURE FILL  
Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features....
US20140302673 Method of Forming Metal Contacts With Low Contact Resistances in a Group III-N HEMT  
Metal contacts with low contact resistances are formed in a group III-N HEMT by forming metal contact openings in the barrier layer of the group III-N HEMT to have depths that correspond to low...
US20120329275 BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS  
A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal...
US20100327443 JOINING STRUCTURE AND A SUBSTRATE-JOINING METHOD USING THE SAME  
The present invention concerns a joining structure and a substrate-joining method using the same. The joining structure comprises a substrate, and comprises a plurality of joining patterns which...
US20150198843 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME  
A display device includes pixels. At least one of the pixels includes a pixel area, a first non-pixel area disposed adjacent to the pixel area and extending in a first direction, and a second...
US20150206944 FORMING A CONDUCTIVE CONNECTION BETWEEN A COMMON ELECTRODE OF AN OPTICAL FRONT PLANE AND AN ELECTRICAL CONTACT PART OF AN OPPOSITE BACK PLANE  
A technique for creating a conductive connection between a contact part (24) of a display back plane (34) and a common electrode (20) of a display front plane (32), comprising the step of...
US20120146736 MEMS VIBRATOR, OSCILLATOR, AND METHOD FOR MANUFACTURING MEMS VIBRATOR  
A MEMS resonator according to the invention includes: a substrate; a first electrode formed above the substrate; and a second electrode having a supporting portion which is formed above the...
US20070010086 Circuit board with a through hole wire and manufacturing method thereof  
An aluminum substrate is drilled to form a first through hole, and is then laminated with copper foils on upper and lower surfaces of the aluminum substrate via a binder. Due to the pressure of...
US20150171008 INTEGRATED CIRCUITS WITH DUMMY CONTACTS AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS  
Integrated circuits with dummy contacts and methods for fabricating such integrated circuits are provided. The method includes forming an interlayer dielectric overlying an electronic component...
US20090091037 Methods for Fabricating Contacts to Pillar Structures in Integrated Circuits  
A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard...
US20130330923 MIDDLE OF LINE STRUCTURES AND METHODS FOR FABRICATION  
A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned...
US20120261829 MIDDLE OF LINE STRUCTURES AND METHODS FOR FABRICATION  
A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned...
US20140149952 TRENCH SILICIDE MASK GENERATION USING DESIGNATED TRENCH TRANSFER AND TRENCH BLOCK REGIONS  
A method for designating TT and TB regions utilizing designated TS regions, without fully generating TT and TB features, and thereafter fabricating TS regions utilizing the designated TT and TB...
US20150097294 METHOD FOR PROCESSING A WAFER AND WAFER STRUCTURE  
A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to...
US20130140704 Low Frequency CMUT with Thick Oxide  
A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the...
US20150262896 EVALUATION ELEMENT AND WAFER  
An evaluation element includes a plurality of first wirings extending in a first direction, connection conductors, each connection conductor electrically contact a single one of the first wirings,...
US20140077384 BIT CELL WITH TRIPLE PATTERNED METAL LAYER STRUCTURES  
An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure...
US20140021626 LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING A LIQUID CRYSTAL DISPLAY DEVICE  
A liquid crystal display device (10) includes: gate wiring (501) formed on a substrate (500) and along a first direction; drain wiring (702) formed on the substrate (500) and along a second...
US20150262912 Via Corner Engineering in Trench-First Dual Damascene Process  
An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the etch stop layer. A via is disposed in...
US20080318419 CHARGE DISSIPATION OF CAVITIES  
Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
US20110208467 CALIBRATION STANDARDS AND METHODS OF THEIR FABRICATION AND USE  
An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of...
US20060281306 Carbon nanotube interconnect contacts  
A method for forming an interconnect on a semiconductor substrate comprises providing at least one carbon nanotube within a trench, etching at least one portion of the carbon nanotube to create an...
US20070272955 Reliable Contacts  
A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation...
US20150056800 Self-aligned interconnects formed using substractive techniques  
A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the...
US20140353835 METHODS OF SELF-FORMING BARRIER INTEGRATION WITH PORE STUFFED ULK MATERIAL  
A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a...
US20110006440 SYSTEM AND METHOD TO REDUCE THE BONDWIRE/TRACE INDUCTANCE  
A method and system for reducing the inductance on an integrated circuit. The method and system comprises providing a first differential line, including a first input and a first output, the first...
US20150200131 TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS BY MODIFIED RF POWER RAMP-UP  
When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be...
US20150076706 THROUGH-SILICON VIA UNIT CELL AND METHODS OF USE  
Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of...
US20150130073 Interconnect Structure and Methods of Forming Same  
A method comprises depositing a first dielectric layer over a substrate, forming a first metal line and a second metal line in the first dielectric layer, wherein the first metal line and the...
US20080150165 SELECTIVE PROCESSING OF SEMICONDUCTOR NANOWIRES BY POLARIZED VISIBLE RADIATION  
Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is...
US20110049578 ELECTRIC COMPONENT AND METHOD OF MANUFACTURING THE ELECTRIC COMPONENT  
According to one embodiment, an electric component includes: a first insulating layer formed on a first wire; a second wire and a functional element formed on the first insulating layer; a second...