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US20100323517 MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE  
Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a...
US20150255330 BARRIER-SEED TOOL FOR FINE-PITCHED METAL INTERCONNECTS  
A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second...
US20140045330 METHODS OF IN-SITU VAPOR PHASE DEPOSITION OF SELF-ASSEMBLED MONOLAYERS AS COPPER ADHESION PROMOTERS AND DIFFUSION BARRIERS  
Embodiments of the present invention provide methods of in-situ vapor phase deposition of self-assembled monolayers as copper adhesion promoters and diffusion barriers. A copper region is formed...
US20130244423 ELECTROLESS GAP FILL  
A method for providing copper filled features is provided. Features are provided in a layer on a substrate. A simultaneous electroless copper plating and anneal is provided. The electroless copper...
US20140302671 Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition  
Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very...
US20120315755 COPPER INTERCONNECT WITH METAL HARDMASK REMOVAL  
A passivation layer is formed on inlaid Cu for protection against oxidation and removal during subsequent removal of an overlying metal hardmask. Embodiments include treating an exposed upper...
US20130299988 GRAPHENE CAP FOR COPPER INTERCONNECT STRUCTURES  
Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of...
US20130270703 ELECTROLESS FILLED CONDUCTIVE STRUCTURES  
Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the...
US20150214158 GATE METAL STRUCTURE AND FORMING METHID OF THE SAME  
A gate metal structure and a forming method of the same are provided. The gate metal structure includes: a substrate and a copper metal layer; and a barrier layer disposed between the substrate...
US20150069625 ULTRA-THIN METAL WIRES FORMED THROUGH SELECTIVE DEPOSITION  
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal...
US20120264292 REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS  
A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier...
US20100295181 REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS  
A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier...
US20130334691 SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS  
A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure...
US20120070981 ATOMIC LAYER DEPOSITION OF A COPPER-CONTAINING SEED LAYER  
The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in...
US20120309190 COPPER INTERCONNECT FORMATION  
Disclosed is a method which includes forming a copper interconnect within a trench or via in a substrate. Forming the copper interconnect includes forming a ruthenium-containing seed layer on a...
US20100038784 REDUNDANT BARRIER STRUCTURE FOR INTERCONNECT AND WIRING APPLICATIONS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE  
A redundant diffusion barrier structure and method of fabricated is provided for interconnect and wiring applications. The structure can also be a design structure. The structure includes a first...
US20100038783 METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE  
A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the...
US20130230983 HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT  
A method of forming a hybrid interconnect structure including dielectric spacers is provided. The method includes forming at least one opening in a dielectric material utilizing a patterned hard...
US20090206484 MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE  
Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a...
US20120276737 POST-ETCHING TREATMENT PROCESS FOR COPPER INTERCONNECTING WIRES  
A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the...
US20100330795 Krypton Sputtering of Low Resistivity Tungsten  
A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be...
US20140035143 METHOD OF REDUCING CONTACT RESISTANCE OF A METAL  
A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the...
US20130309863 METHODS OF FORMING COPPER-BASED CONDUCTIVE STRUCTURES BY FORMING A COPPER-BASED SEED LAYER HAVING AN AS-DEPOSITED THICKNESS PROFILE AND THEREAFTER PERFORMING AN ETCHING PROCESS AND ELECTROLESS COPPER DEPOSITION  
Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating...
US20110070730 SEQUENTIAL DEPOSITION OF TANTALUM NITRIDE USING A TANTALUM-CONTAINING PRECURSOR AND A NITROGEN-CONTAINING PRECURSOR  
Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum...
US20140106562 Barrier Layer for Copper Interconnect  
A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary...
US20100304562 ELECTROLESS DEPOSITION OF COBALT ALLOYS  
Systems and methods for electroless deposition of a cobalt-alloy layer on a copper surface include a solution characterized by a low pH. This solution may include, for example, a cobalt(II) salt,...
US20120205793 SEED LAYER PASSIVATION  
A method of processing a microfeature workpiece generally includes depositing a first conducting layer, at least partially reducing oxides on the first conducting layer to provide a reduced first...
US20100311236 COPPER INTERCONNECT STRUCTURE WITH AMORPHOUS TANTALUM IRIDIUM DIFFUSION BARRIER  
A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier...
US20130050883 INTEGRATED ADVANCE COPPER FUSE COMBINED WITH ESD/OVER-VOLTAGE/REVERSE POLARITY PROTECTION  
In one embodiment, an integrated circuit, and method of manufacturing thereof, is provided. The integrated circuit contains an over-voltage protection element and an over-current protection...
US20150214093 PROCESSES AND SYSTEMS FOR ENGINEERING A BARRIER SURFACE FOR COPPER DEPOSITION  
A method for processing an interconnect structure on a substrate is provided, including: depositing a metallic barrier layer to line the interconnect structure, the metallic barrier layer...
US20110143533 POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS  
A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in...
US20150076697 DUMMY BARRIER LAYER FEATURES FOR PATTERNING OF SPARSELY DISTRIBUTED METAL FEATURES ON THE BARRIER WITH CMP  
A semiconductor device comprises a plurality of device features formed on a substrate and a plurality of dummy features formed on the substrate and across an open region between the device...
US20070259520 Beveled trench forming device for concrete slab foundations  
An assemblage which form a beveled edge in a slab-on-grade foundation trench. The device is comprised of straight members corner members, and a connector member to hold the larger members...
US20150024588 Hard Mask Removal Scheme  
A method includes forming a barrier layer in a via hole and over a hard mask layer. The hard mask layer is disposed over a dielectric layer. The via hole is located through the dielectric layer...
US20150162240 TRENCH FORMATION USING ROUNDED HARD MASK  
A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench...
US20120007231 METHOD OF FORMING CU PILLAR CAPPED BY BARRIER LAYER  
A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper...
US20140045331 SELF-ALIGNED BARRIER AND CAPPING LAYERS FOR INTERCONNECTS  
An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper...
US20140191329 METHOD FOR PRODUCING METAL CONTACTS WITHIN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT  
An integrated circuit includes a MOS transistor having a gate region and source and drain regions separated from the gate region by insulating spacers. At least two metal contact pads respectively...
US20150255331 INTEGRATED CIRCUITS WITH A COPPER AND MANGANESE COMPONENT AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS  
Integrated circuits with copper and magnesium components and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming an aperture...
US20140027822 Copper Contact Plugs with Barrier Layers  
A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An...
US20140319685 Hybrid Graphene-Metal Interconnect Structures  
Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene...
US20150147879 ULTRA-THIN STRUCTURE TO PROTECT COPPER AND METHOD OF PREPARATION  
Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of...
US20130164933 HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS  
An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for...
US20140213051 Hybrid Interconnect Scheme and Methods for Forming the Same  
A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k...
US20120273950 INTEGRATED CIRCUIT STRUCTURE INCLUDING COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME  
An integrated circuit structure including a copper-aluminum interconnect with a CuSiN layer and a method for fabricating the same are provided. The method for fabricating an integrated circuit...
US20140273436 METHODS OF FORMING BARRIER LAYERS FOR CONDUCTIVE COPPER STRUCTURES  
One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in at least the trench/via, after forming said barrier layer,...
US20120289043 METHOD FOR FORMING DAMASCENE TRENCH STRUCTURE AND APPLICATIONS THEREOF  
A method for fabricating a damascene trench structure, wherein the method comprises steps as follows: A semiconductor structure having an inner layer dielectric (ILD) and a patterned hard mask...
US20140273437 SUBTRACTIVE PLASMA ETCHING OF A BLANKET LAYER OF METAL OR METAL ALLOY  
A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch...
US20110306203 INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING A DAMASCENE STRUCTURE  
An interconnect structure is provided, including a layer of dielectric material having at least one opening and a first barrier layer on sidewalls defining the opening. A ruthenium-containing...
US20150048508 NANOWIRES COATED ON TRACES IN ELECTRONIC DEVICES  
Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first...